Forum: FPGA, VHDL & Verilog ADC/DAC Spartan 3E VHDL code problem

Author: Irati (Guest)
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Dear All,

I am currently implementing an ADC/func/DAC on the Spartan 3e Starter 
Kit board. It basicly reads the analog signal, converts it into a 
digital signal, apllies a multiplication and converts the result back to 
an analog signal. The code is written on VHDL and compiled on ISE Design 
Suite 14.6. Please find attached the main code, the ucf file and the 
simulation file. I am simulating on Isim.

I have tried to simulate some parts of the implementation and it seems 
to work but because of the analog input and output signals, I am having 
troubles to really track the code on the implementation.

Could anybody have a look at it and tell me what I am doing wrong? As 
far as I understand, the steps the ADC/func/DAC should follow are:

i)   Set the gain of the amplifier through spi_mosi.
ii)  Get the converted digital values from the ADC through spi_miso.
iii)  Apply the *2 to the digital value.
iv)  Send the digital result to the DAC through the spi_mosi.

Any help or advice will be really appreciated. Thanks a lot!


Author: Lothar Miller (lkmiller) (Moderator)
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Why doing all steps at once? I would generate a sawtooth signal (its 
just a counter) and output this signal to the DAC. Then its fairly easy 
to check out this part of the design...

Author: Irati (Guest)
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Well, as I understand it, it does one step after the other with the 
risingedge of the divided clock so it is the same as having a counter, 
isnt it?

Author: Jürgen S. (engineer)
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The treatment of the add_counter is a bit strange and it does not appear 
to be complete. I also wonder about this construction:

SPI_SCK <= risingedge;

Did you respect the CLK/DATA relation correctly?


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