----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:03:00 08/19/2017 
-- Design Name: 
-- Module Name:    Top_Dac - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Top_Dac is
    Port (	CLK_50MHz 		: in  STD_LOGIC;
				-------------SPI singal declarations-------------
				SPI_SEL			: out std_logic;         -- Chip Select
				SPI_SCK			: out std_logic;         -- Serial Clock
				RESET_IN			: in  std_logic;         -- Reset Switch
				RESET_OUT		: out std_logic;
				SPI_DIN			: in 	std_logic;        -- Data Read
				SPI_DOUT			: out std_logic;			-- Data Send
				SPI_LDAC			: out std_logic;
				Rd_out			: out std_logic
				
--				-------------UART Interface----------------------
--				FPGA_UART_TX	: out std_logic;
--				FPGA_UART_RX	: in 	std_logic;
--				-------------LED Signal Declarations-------------
--				LED				: out std_logic_vector(7 downto 0)				
		);
end Top_Dac;

architecture Behavioral of Top_Dac is

signal reset1 : Std_logic;
signal done1 : STD_LOGIC;

component clock_20
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		c0				: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
end component;

	
	COMPONENT Reg_Data_Set
	PORT(
		clk : IN std_logic;          
		rst : in std_logic;
		spi_en : OUT std_logic;
		spi_data : OUT std_logic_vector(15 downto 0);
		done : OUT std_logic;
		spi_addr : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;
	
	
	COMPONENT DAC8775_SPI
	PORT(
		clk : IN std_logic;
		rst : IN std_logic;
		en : IN std_logic;
		spi_din : IN std_logic;
		spi_addr : IN std_logic_vector(7 downto 0);
		spi_data : IN std_logic_vector(15 downto 0);
		done2 : IN std_logic;          
		spi_clk : OUT std_logic;
		spi_en : OUT std_logic;
		ldac : OUT std_logic;
		spi_dout : OUT std_logic;
		spi_rd_data : OUT std_logic_vector(15 downto 0);
		data_rdy : OUT std_logic
		);
	END COMPONENT;

--	signal wait_st1			: STD_LOGIC;
	signal Clock_40MHz_wire : std_logic;
	signal locked_wire		: std_logic;
	signal Reset_Reg_data	: std_logic :='1';
	signal En_Reg_data		: std_logic;
	signal Data_Reg_data		: std_logic_vector(15 downto 0);
	signal address_Reg_data	: std_logic_vector(7 downto 0);	
	signal spi_rd_data		: std_logic_vector(15 downto 0);
	signal spi_data_rdy		: std_logic;
	signal spi_din_top		: std_logic;
	signal spi_clk_top		: std_logic;
	signal spi_en_top			: std_logic;
	signal spi_dout_top		: std_logic;
	
Begin
--U0 : Clock_40MHz port map
--(
--	  -- Clock in ports
--    CLK_IN1 => CLK_50MHz,
--    -- Clock out ports
--    CLK_OUT1 => Clock_40MHz_wire,
--    -- Status and control signals
--    RESET  => '0',
--    LOCKED => locked_wire 
--	 );
	clock_20_inst : clock_20 PORT MAP (
		areset	 => '0',
		inclk0	 => CLK_50MHz,
		c0			 => Clock_40MHz_wire,
		locked	 => locked_wire
	);

										
	Inst_Reg_Data_Set: Reg_Data_Set PORT MAP(
		clk =>  Clock_40MHz_wire,
		rst => Reset_Reg_data,
		spi_en => En_Reg_data,
		spi_data =>Data_Reg_data ,
		done =>done1 ,
		spi_addr => address_Reg_data
	);


								
	
Inst_DAC8775_SPI: DAC8775_SPI PORT MAP(
										clk			=>	Clock_40MHz_wire,										
										rst			=> Reset_Reg_data,
										en				=> En_Reg_data,
										spi_din		=> SPI_DIN,				--spi_din_top,
										spi_clk		=> SPI_SCK,				--spi_clk_top,
										spi_en		=> SPI_SEL,				--spi_en_top,
										ldac			=> SPI_LDAC,				--LDAC signal,
										spi_dout		=> SPI_DOUT,			--spi_dout_top,
										spi_addr		=> address_Reg_data,
										spi_data		=> Data_Reg_data,
--									   wait_sts 	=> wait_st1,
										spi_rd_data	=> open,
										data_rdy		=> open,
										done2       => done1
	);

							 
--SPI_DIN <= spi_dout_top;
--SPI_SCK <= spi_clk_top;
--SPI_SEL <= spi_en_top;
--SPI_DOUT<= spi_din_top;								
						RESET_OUT <= RESET_IN;
						Rd_out <= SPI_DIN;
						Reset_Reg_data <= RESET_IN;
end Behavioral;