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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:04:18 08/19/2017 
-- Design Name: 
-- Module Name:    DAC8775_SPI - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:03:30 02/06/2014 
-- Design Name: 
-- Module Name:    AD9361_SPI - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC8775_SPI is
Port(	clk,en		: in std_logic;              	-- System Clock
         rst		:  in std_logic;
		spi_din 		: in std_logic;
		spi_clk 		: out std_logic;					-- SPI Clock
		spi_en 		: out std_logic;
		ldac			: out std_logic; 					--LDAC signal
		spi_dout 	: out std_logic;
		spi_addr 	: in std_logic_vector (7 downto 0);
		spi_data 	: in std_logic_vector (15 downto 0);
		spi_rd_data : out std_logic_vector (15 downto 0);
		data_rdy 	: out std_logic;
		done2			: in std_logic
	 );
end DAC8775_SPI;

architecture Behavioral of DAC8775_SPI is

type states is (idle, start_spi,write_high, write_low, read_high, read_low, rd_data_high, rd_data_low,write_low_end,write_high_end,rd_data_low_end, finish);
signal c_s,n_s : states;

signal count 			: integer range 0 to 24;
signal rd_count 		: integer range 0 to 24;
signal addr_temp 		: std_logic_vector (7 downto 0);
signal rd_data_temp 	: std_logic_vector (15 downto 0);
signal wr_data_temp 	: std_logic_vector (15 downto 0);
signal send_temp 		: std_logic_vector (23 downto 0);

--attribute KEEP : string;
--attribute KEEP of spi_addr		: signal is "TRUE";


begin
process(clk,rst)
begin
	If rising_edge (clk) then
		if (rst='1') then
			spi_clk 			<='0';
			spi_en 			<='1';
			ldac				<='0';
			spi_dout 		<='0';
			spi_rd_data 	<= (others=>'0');
			data_rdy 		<= '0';
			count 			<= 23;
			rd_count 		<= 0;
			rd_data_temp 	<= (others=>'0');
			addr_temp 		<= spi_addr;
			send_temp 		<= addr_temp & wr_data_temp;
			wr_data_temp 	<= spi_data;
			data_rdy 		<='0';
		if(rst='0') then
			c_s <= n_s;
			case n_s is
				when idle =>
					spi_clk 			<='0';
					spi_en 			<='1';
					ldac				<='0';
					spi_dout 		<='0';
					addr_temp 		<= spi_addr;
					wr_data_temp 	<= spi_data;
					spi_rd_data 	<= rd_data_temp;
					send_temp 		<= addr_temp & wr_data_temp;
					count 			<= 23;
					rd_count 		<= 15;
					data_rdy 		<= '1';
					
				when start_spi =>
					send_temp 	<= addr_temp & wr_data_temp;
					count 		<= 23;
					rd_count 	<= 15;
					spi_en 		<='0';
					ldac			<='1';

				when write_high =>
					spi_clk 	<='1';
					spi_dout <= send_temp(count);
					
				when write_low =>
					spi_clk 	<='0';
					count 	<= count -1;
					
				when write_high_end =>
					spi_clk 	<= '1';
					spi_dout <= send_temp(count);

				when write_low_end =>
					spi_clk <='0';
					

				when read_high =>
					spi_clk 	<='1';
					spi_dout <= send_temp(count);
					data_rdy <='0';				
				when read_low =>
					spi_clk 	<='0';
					spi_dout <= send_temp(count);
					count 	<= count - 1;
					data_rdy <='0';

				when rd_data_high=>
					spi_clk 	<='1';
					spi_dout <= '0';
					rd_data_temp(rd_count)<= spi_din;
					data_rdy <='0';
					
				when rd_data_low =>
					spi_clk 	<='0';
					rd_count <= rd_count-1;
					data_rdy <='0';
					
				when rd_data_low_end =>
					spi_clk 	<='0';
					data_rdy <='0';
					
				when finish =>
					spi_en <= '1';

				when others =>
					spi_clk 			<='0';
					spi_en 			<='1';
					ldac				<='0';
					spi_dout 		<='0';
					spi_rd_data 	<= (others=>'0');
					data_rdy 		<= '0';
					count 			<= 23;
					rd_count 		<= 0;
					rd_data_temp 	<= (others=>'0');
					addr_temp 		<= (others =>'0');
					wr_data_temp 	<= (others =>'0');
					send_temp 		<= (others =>'0');
					data_rdy 		<='0';
			
			end case;
		end if;
	End If;
end process;
	
-----------STATE MACHINE OPERATION-----------

process (c_s,en,addr_temp,count,rd_count )
begin
	n_s <= c_s;
	
	case c_s is
	
		when idle =>
			if (en='1' and done2='0') then
				n_s <= start_spi;
			elsif(en='0' and done2='0') then 
				n_S <= idle;
			elsif(en='1' and done2='1') then 
				n_S <= finish;
			elsif(en='0' and done2='1') then
				n_S <= finish;
			end if;

		when start_spi => 
			if (addr_temp(7)='0') then
				n_s <= write_high;
			else
				n_s <= read_high;
			end if;

		when write_high =>
				n_s <= write_low;
			
		when write_low =>
			if (count =0) then
				n_s <= write_high_end;
			else
				n_s <= write_high;
			end if;
			
		when write_high_end =>
			n_s <=write_low_end;
			
		when write_low_end =>
			n_s <= idle;

		when read_high =>
				n_s <= read_low;
			
		when read_low =>
			if (count <= 15) then
				n_s <= rd_data_high;
			else
				n_s <= read_high;
			end if;

		when rd_data_high =>
			if (rd_count <= 0) then
				n_s <= rd_data_low_end;
			else
				n_S <= rd_data_low;
			end if;

		when rd_data_low =>
			n_s <= rd_data_high;
			
		when rd_data_low_end =>
				n_s <= idle;
--			else
--				n_s <= finish;
--			end if;
		
		when finish =>
			if (done2 = '1') then
				n_s <= finish;
--			else
--				n_s <= idle;
			end if;	
			
	when others =>
	n_s <= finish;

		end case;
end process;	

end Behavioral;