// test.v
`define N 10     // Resolution of effective DPWM 
`define M 4      // Resolution of core DPWM

module test (clk,d,outadder,dlr,b,q,ed,c,c1);

input [`N-1:0] d;
input clk;
output reg[`N-1:0] outadder;
output reg [`M-1:0] dlr;

output reg [5:0] b ;
output reg [5:0] q ;
output reg [5:0] ed;
output reg [6:0] c ;
output reg [9:0] c1 ;

reg [7:0] marray [0:1];

initial
begin
    $readmemb("init.dat", marray);
    b = marray[0];
    c1= marray[0];
 //   ed= marray[0];
    q = marray[0];
    c = marray[0];
//    $display ("b= %b",b);
//    $display ("q= %b",q);
//    $display ("c= %b",c);
end

always @(clk or d or b or c)
begin
    outadder = d + b + c;
    dlr = outadder[`N-1:6];
    ed = outadder[5:0];
end

always @(posedge clk)
begin
    c1 = c1+1;   
    q <= ed;
    b[5:0] <= q; 
   // b[9:6] <= 0; 
end

always @(q)
begin
    c[0] <= 0;
    c[6:1] <= q;
//    c[9:7] <= 0;  
end
endmodule