`define TB_ABORT (3'b000)
`define TB_ONCE (3'b001)
`define TB_DONE (3'b010)
`define TB_LOOPING (3'b011)
`define TB_RESTART (3'b100)
`define TB_END (3'b101)
`timescale  1 ns /  1 ps

module stimulus(clk, d, outadder, dlr, b, q, ed, c, c1);
  output clk;
  output [9:0] d;
  input [9:0] outadder;
  input [3:0] dlr;
  input [5:0] b;
  input [5:0] q;
  input [5:0] ed;
  input [6:0] c;
  input [9:0] c1;
  reg clk_driver;
  reg [9:0] d_driver;
  assign clk = clk_driver;
  assign d = d_driver;


  // Control Signal Declarations
  reg [2:0] tb_status;


  // The following initial block will start up the stimulator.
  initial
    begin
    tb_status <= `TB_ONCE;
    Unclocked;
    tb_status <= `TB_DONE;
    $display("Note: At %t: End of stimulus reached.  Use End Diagram Marker to extend or shorten stimulus.", $time);
    end

  // Clocked Sequences

  // Sequence: Unclocked

  // Drive signals to their initial values
  initial
    begin
    clk_driver <= 1'b0;
    d_driver <= 10'b1100010111;
    end

  task Unclocked;
    begin
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #41;
    d_driver <= 10'b1111111111;
    d_driver <= 10'b0101010101;
    #9;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #8;
    d_driver <= 10'bxxxxxxxxxx;
    d_driver <= 10'b0000100000;
    #42;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    clk_driver <= 1'b0;
    #50;
    clk_driver <= 1'b1;
    #50;
    end
  endtask
endmodule

// Test Bench wrapper for stimulus and Model Under Test

module testbench;
  wire clk;
  wire [9:0] d;
  wire [9:0] outadder;
  wire [3:0] dlr;
  wire [5:0] b;
  wire [5:0] q;
  wire [5:0] ed;
  wire [6:0] c;
  wire [9:0] c1;

  // Stimulator instance
  stimulus stimulus_0(.clk(clk),
            .d(d),
            .outadder(outadder),
            .dlr(dlr),
            .b(b),
            .q(q),
            .ed(ed),
            .c(c),
            .c1(c1));

  // Instantiation of Model Under Test.
  test test_0(.clk(clk),
            .d(d),
            .outadder(outadder),
            .dlr(dlr),
            .b(b),
            .q(q),
            .ed(ed),
            .c(c),
            .c1(c1));
endmodule