`define N 10 // Resolution of effective DPWM `define M 4 // Resolution of core DPWM module test (clk,d,outadder,dlr,b,q,ed,c,c1); input [`N-1:0] d; input clk; output reg[`N-1:0] outadder; output reg [`M-1:0] dlr; output reg [5:0] b = 0 ; output reg [5:0] q = 0; output reg [5:0] ed; output reg [6:0] c =0 ; output reg [9:0] c1 =0; always @(clk or d or b or c) begin outadder = d + b + c; ed = outadder[5:0]; dlr = outadder[`N-1:6]; end always @(posedge clk) begin c1 = c1+1; q <= ed; b[5:0] <= q; // b[9:6] <= 0; end always @(q) begin c[0] <= 0; c[6:1] <= q; // c[9:7] <= 0; end endmodule