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Forum: FPGA, VHDL & Verilog Finite State Machine working in simulation, but not working on actual FPGA board


von vhdl n. (Company: none) (pranoy)


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hi guys,

i've written the following code as a control unit for my project (FPGA 
implementation of a functional microcontroller).

the code is working in simulation using modelsim.

also it is synthesised using xilinx.

but when i program it on an actual FPGA(spatan 3) i'm not getting 
correct working.

the part which is not working is when i give the IN instruction.

for entering a data the in_s state will continue until the enter pin has 
a low to high transition. (refer lines 104 to 110 of program)

but it is not working.

the in_s state is continuing infinitely.

please help me with this.

Thanks in advance.
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity mealy is
5
port (clk : in std_logic;
6
      reset : in std_logic;
7
      enter : in std_logic;
8
      input:in std_logic_vector(3 downto 0);
9
      output:out std_logic_vector(3 downto 0);
10
      pc_enable: out std_logic;
11
      alu_enable: out std_logic;
12
      rom_enable: out std_logic;
13
      reg_enable: out std_logic;
14
      ir_enable: out std_logic;
15
      load_a:out std_logic_vector(2 downto 0);
16
      load_b:out std_logic_vector(2 downto 0);
17
      pc_reset:out std_logic;
18
      a_zero_status:in std_logic;
19
      sel: out std_logic
20
  );
21
end mealy;
22
23
architecture behavioral of mealy is
24
25
type state_type is (fetch,decode,add_s,sub_s,mov_ab_s,and_s,or_s,mov_ba_s,in_s,out_s,jmp_s,jnz_s,jz_s,inc_s,dec_s,halt_s,rab,wa,wb,ra,nop_s);  --type of state machine.
26
signal current_s,next_s: state_type;  --current and next state declaration.
27
28
begin
29
30
process (clk,reset)
31
begin
32
 if (reset='1') then
33
  current_s <= fetch;  --default state on reset.
34
  pc_reset<='1';
35
elsif (rising_edge(clk)) then
36
  current_s <= next_s;   --state change.
37
  pc_reset<='0';
38
end if;
39
end process;
40
41
--state machine process.
42
process (current_s,enter,input,a_zero_status)
43
begin
44
  case current_s is
45
    
46
    when fetch =>        --when current state is "fetch"
47
    next_s <= decode;
48
       
49
    when decode =>       --when current state is "decode"
50
    if(input ="0000") then
51
    next_s <= rab;
52
    elsif(input ="0001") then
53
    next_s <= rab;
54
    elsif(input ="0010") then
55
    next_s <= rab;
56
    elsif(input ="0011") then
57
    next_s <= rab;
58
    elsif(input ="0100") then
59
    next_s <= rab;
60
    elsif(input ="0101") then
61
    next_s <= ra;
62
    elsif(input ="0110") then
63
    next_s <= in_s;
64
    elsif(input ="0111") then
65
    next_s <= ra;
66
    elsif(input ="1000") then
67
    next_s <= jmp_s;
68
    elsif(input ="1001") then
69
    next_s <= jnz_s;
70
    elsif(input ="1010") then
71
    next_s <= jz_s;
72
    elsif(input ="1011") then
73
    next_s <= nop_s;
74
    elsif(input ="1100") then
75
    next_s <= rab;
76
    elsif(input ="1101") then
77
    next_s <= rab;
78
    elsif(input ="1111") then
79
    next_s <= halt_s;
80
    
81
    else
82
    next_s<=decode;
83
    end if;
84
85
86
    when add_s =>         --when current state is "add_s"
87
    next_s <= wa;
88
    
89
    when sub_s =>         --when current state is "sub_s"
90
    next_s <= wa;
91
    
92
    when mov_ab_s =>         --when current state is "mov_ab_s"
93
    next_s <= wa;
94
    
95
    when and_s =>         --when current state is "and_s"
96
    next_s <= wa;
97
    
98
    when or_s =>         --when current state is "or_s"
99
    next_s <= wa;
100
    
101
    when mov_ba_s =>         --when current state is "mov_ba_s"
102
    next_s <= wb;
103
    
104
    when in_s =>         --when current state is "in_s"
105
    enter_r<=enter;
106
    if(enter_r='0' and enter='1') then
107
    next_s <= fetch;
108
    else
109
    next_s <= in_s;
110
    end if;
111
    
112
    when out_s =>         --when current state is "out_s"
113
    next_s <= fetch;
114
    
115
    when jmp_s =>         --when current state is "jmp_s"
116
    next_s <= fetch;
117
    
118
    when jnz_s =>         --when current state is "jnz_s"
119
    next_s <= fetch;
120
    
121
    when jz_s =>         --when current state is "jz_s"
122
    next_s <= fetch;
123
    
124
    when nop_s =>         --when current state is "nop_s"
125
    next_s <= fetch;
126
    
127
    when inc_s =>         --when current state is "inc_s"
128
    next_s <= wa;
129
    
130
    when dec_s =>         --when current state is "dec_s"
131
    next_s <= wa;
132
    
133
    when halt_s =>         --when current state is "halt_s"
134
    next_s <= halt_s;
135
136
    when rab =>       --when current state is "rab"
137
    if(input ="0000") then
138
    next_s <= add_s;
139
    elsif(input ="0001") then
140
    next_s <= sub_s;
141
    elsif(input ="0010") then
142
    next_s <= mov_ab_s;
143
    elsif(input ="0011") then
144
    next_s <= and_s;
145
    elsif(input ="0100") then
146
    next_s <= or_s;
147
    elsif(input ="1100") then
148
    next_s <= inc_s;
149
    elsif(input ="1101") then
150
    next_s <= dec_s;
151
    
152
    end if;
153
    
154
    when wa =>         --when current state is "wa"
155
    next_s <= fetch;
156
    
157
    when wb =>         --when current state is "wb"
158
    next_s <= fetch;
159
    
160
    when ra =>         --when current state is "wb"
161
    if(input ="0101") then
162
    next_s <= mov_ba_s;
163
    elsif(input ="0111") then
164
    next_s <= out_s;
165
    end if;
166
    
167
         
168
end case;
169
end process;
170
    
171
    output_logic:process(current_s)
172
    begin
173
        case current_s is
174
            
175
        when fetch=>
176
                pc_enable<='1';
177
                alu_enable<='0';
178
                rom_enable<='1';
179
                reg_enable<='0';
180
                ir_enable<='0';
181
                load_a<="UUU";
182
                load_b<="UUU";
183
                sel<='U';
184
                
185
        when decode=>
186
                pc_enable<='0';
187
                alu_enable<='0';
188
                rom_enable<='0';
189
                reg_enable<='0';
190
                ir_enable<='1';
191
                load_a<="UUU";
192
                load_b<="UUU";
193
                sel<='U';
194
                
195
          when add_s=>
196
                pc_enable<='0';
197
                alu_enable<='1';
198
                rom_enable<='0';
199
                reg_enable<='0';
200
                ir_enable<='0';
201
                load_a<="UUU";
202
                load_b<="UUU";
203
                sel<='U';
204
                output<="0000";
205
                
206
          when sub_s=>
207
                pc_enable<='0';
208
                alu_enable<='1';
209
                rom_enable<='0';
210
                reg_enable<='0';
211
                ir_enable<='0';
212
                load_a<="UUU";
213
                load_b<="UUU";
214
                sel<='U';
215
                output<="0001";
216
                
217
         when mov_ab_s=>
218
                pc_enable<='0';
219
                alu_enable<='1';
220
                rom_enable<='0';
221
                reg_enable<='0';
222
                ir_enable<='0';
223
                load_a<="110";
224
                load_b<="110";
225
                sel<='0';
226
                output<="0010";
227
                
228
        when and_s=>
229
                pc_enable<='0';
230
                alu_enable<='1';
231
                rom_enable<='0';
232
                reg_enable<='0';
233
                ir_enable<='0';
234
                load_a<="UUU";
235
                load_b<="UUU";
236
                sel<='U';
237
                output<="0011";
238
                
239
        when or_s=>
240
                pc_enable<='0';
241
                alu_enable<='1';
242
                rom_enable<='0';
243
                reg_enable<='0';
244
                ir_enable<='0';
245
                load_a<="UUU";
246
                load_b<="UUU";
247
                sel<='U';
248
                output<="0100";
249
                
250
        when mov_ba_s=>
251
                pc_enable<='0';
252
                alu_enable<='1';
253
                rom_enable<='0';
254
                reg_enable<='0';
255
                ir_enable<='0';
256
                load_a<="UUU";
257
                load_b<="UUU";
258
                sel<='U';
259
                output<="0101";
260
                
261
        when in_s=>
262
                pc_enable<='0';
263
                alu_enable<='0';
264
                rom_enable<='0';
265
                reg_enable<='1';
266
                ir_enable<='0';
267
                load_a<="110";
268
                load_b<="UUU";
269
                sel<='1'; 
270
                output<="0110";
271
                
272
        when out_s=>
273
                pc_enable<='0';
274
                alu_enable<='1';
275
                rom_enable<='0';
276
                reg_enable<='0';
277
                ir_enable<='0';
278
                load_a<="UUU";
279
                load_b<="UUU";
280
                sel<='0';
281
                output<="0111";
282
                
283
        when jmp_s=>
284
                pc_enable<='0';
285
                alu_enable<='0';
286
                rom_enable<='0';
287
                reg_enable<='0';
288
                ir_enable<='0';
289
                load_a<="UUU";
290
                load_b<="UUU";
291
                sel<='0';
292
                output<="1000";
293
                
294
        when jnz_s=>
295
                pc_enable<='0';
296
                alu_enable<='0';
297
                rom_enable<='0';
298
                reg_enable<='0';
299
                ir_enable<='0';
300
                load_a<="UUU";
301
                load_b<="UUU";
302
                sel<='0';
303
                output<="1001";
304
                
305
        when jz_s=>
306
                pc_enable<='0';
307
                alu_enable<='0';
308
                rom_enable<='0';
309
                reg_enable<='0';
310
                ir_enable<='0';
311
                load_a<="UUU";
312
                load_b<="UUU";
313
                sel<='0';
314
                output<="1010";
315
                
316
        when nop_s=>
317
                pc_enable<='0';
318
                alu_enable<='0';
319
                rom_enable<='0';
320
                reg_enable<='0';
321
                ir_enable<='0';
322
                load_a<="UUU";
323
                load_b<="UUU";
324
                sel<='0';
325
                output<="1011";
326
                
327
        when inc_s=>
328
                pc_enable<='0';
329
                alu_enable<='1';
330
                rom_enable<='0';
331
                reg_enable<='0';
332
                ir_enable<='0';
333
                load_a<="UUU";
334
                load_b<="UUU";
335
                sel<='U';
336
                output<="1100";
337
                
338
        when dec_s=>
339
                pc_enable<='0';
340
                alu_enable<='1';
341
                rom_enable<='0';
342
                reg_enable<='0';
343
                ir_enable<='0';
344
                load_a<="UUU";
345
                load_b<="UUU";
346
                sel<='U';
347
                output<="1101";
348
                
349
        when halt_s=>
350
                pc_enable<='0';
351
                alu_enable<='1';
352
                rom_enable<='0';
353
                reg_enable<='1';
354
                ir_enable<='0';
355
                load_a<="101";
356
                load_b<="UUU";
357
                sel<='U';
358
                output<="0111";
359
                
360
         when wa=>
361
                pc_enable<='0';
362
                alu_enable<='0';
363
                rom_enable<='0';
364
                reg_enable<='1';
365
                ir_enable<='0';
366
                load_a<="110";
367
                load_b<="UUU";
368
                sel<='0';
369
                
370
          when wb=>
371
                pc_enable<='0';
372
                alu_enable<='0';
373
                rom_enable<='0';
374
                reg_enable<='1';
375
                ir_enable<='0';
376
                load_a<="UUU";
377
                load_b<="110";
378
                sel<='U';
379
                
380
          when rab=>
381
                pc_enable<='0';
382
                alu_enable<='0';
383
                rom_enable<='0';
384
                reg_enable<='1';
385
                ir_enable<='0';
386
                load_a<="101";
387
                load_b<="101";
388
                sel<='0';
389
                
390
        when ra=>
391
                pc_enable<='0';
392
                alu_enable<='0';
393
                rom_enable<='0';
394
                reg_enable<='1';
395
                ir_enable<='0';
396
                load_a<="101";
397
                load_b<="UUU";
398
                sel<='U';
399
                                    
400
  end case;
401
end process;
402
403
end behavioral;

: Edited by User
von daniel__m (Guest)


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vhdl newbie wrote:

> elsif (rising_edge(clk)) then
>   current_s <= next_s;   --state change.
>   pc_reset<='0';
> end if;
...
> when in_s =>         --when current state is "in_s"
>     if rising_edge(enter) then
>     next_s <= fetch;
>     else
>     next_s <= in_s;
>     end if;

this is a very ugly way to describe hardware and is a complex type of 
gated clock! I wonder, that this gets synthesized.

I disbelieve, that even the simulation works completely. The state 
machine would only switch, if two signal edges occures at the same time: 
clk and enter. This is a infinity small time window.

The usual way is to capture the enter signal and compare the captured 
signal with the actual value.

von vhdl n. (Company: none) (pranoy)


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sir thanks for your reply.

i've edited my code and is posting it now.

the previous code was a wrong code and was not the code which i wanted.

posting the actual code here.

1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity mealy is
5
port (clk : in std_logic;
6
      reset : in std_logic;
7
      enter : in std_logic;
8
      input:in std_logic_vector(3 downto 0);
9
      output:out std_logic_vector(3 downto 0);
10
      pc_enable: out std_logic;
11
      alu_enable: out std_logic;
12
      rom_enable: out std_logic;
13
      reg_enable: out std_logic;
14
      ir_enable: out std_logic;
15
      load_a:out std_logic_vector(2 downto 0);
16
      load_b:out std_logic_vector(2 downto 0);
17
      pc_reset:out std_logic;
18
      a_zero_status:in std_logic;
19
      sel: out std_logic
20
  );
21
end mealy;
22
23
architecture behavioral of mealy is
24
25
type state_type is (fetch,decode,add_s,sub_s,mov_ab_s,and_s,or_s,mov_ba_s,in_s,out_s,jmp_s,jnz_s,jz_s,inc_s,dec_s,halt_s,rab,wa,wb,ra,nop_s);  --type of state machine.
26
signal current_s,next_s: state_type;  --current and next state declaration.
27
signal enter_r:std_logic;
28
29
begin
30
31
process (clk,reset)
32
begin
33
 if (reset='1') then
34
  current_s <= fetch;  --default state on reset.
35
  pc_reset<='1';
36
elsif (rising_edge(clk)) then
37
  current_s <= next_s;   --state change.
38
  pc_reset<='0';
39
end if;
40
end process;
41
42
--state machine process.
43
process (current_s,enter,input,a_zero_status)
44
begin
45
  case current_s is
46
    
47
    when fetch =>        --when current state is "fetch"
48
    next_s <= decode;
49
       
50
    when decode =>       --when current state is "decode"
51
    if(input ="0000") then
52
    next_s <= rab;
53
    elsif(input ="0001") then
54
    next_s <= rab;
55
    elsif(input ="0010") then
56
    next_s <= rab;
57
    elsif(input ="0011") then
58
    next_s <= rab;
59
    elsif(input ="0100") then
60
    next_s <= rab;
61
    elsif(input ="0101") then
62
    next_s <= ra;
63
    elsif(input ="0110") then
64
    next_s <= in_s;
65
    elsif(input ="0111") then
66
    next_s <= ra;
67
    elsif(input ="1000") then
68
    next_s <= jmp_s;
69
    elsif(input ="1001") then
70
    next_s <= jnz_s;
71
    elsif(input ="1010") then
72
    next_s <= jz_s;
73
    elsif(input ="1011") then
74
    next_s <= nop_s;
75
    elsif(input ="1100") then
76
    next_s <= rab;
77
    elsif(input ="1101") then
78
    next_s <= rab;
79
    elsif(input ="1111") then
80
    next_s <= halt_s;
81
    
82
    else
83
    next_s<=decode;
84
    end if;
85
86
87
    when add_s =>         --when current state is "add_s"
88
    next_s <= wa;
89
    
90
    when sub_s =>         --when current state is "sub_s"
91
    next_s <= wa;
92
    
93
    when mov_ab_s =>         --when current state is "mov_ab_s"
94
    next_s <= wa;
95
    
96
    when and_s =>         --when current state is "and_s"
97
    next_s <= wa;
98
    
99
    when or_s =>         --when current state is "or_s"
100
    next_s <= wa;
101
    
102
    when mov_ba_s =>         --when current state is "mov_ba_s"
103
    next_s <= wb;
104
    
105
    when in_s =>         --when current state is "in_s"
106
    enter_r<=enter;
107
    if(enter_r='0' and enter='1') then
108
    next_s <= fetch;
109
    else
110
    next_s <= in_s;
111
    end if;
112
    
113
    when out_s =>         --when current state is "out_s"
114
    next_s <= fetch;
115
    
116
    when jmp_s =>         --when current state is "jmp_s"
117
    next_s <= fetch;
118
    
119
    when jnz_s =>         --when current state is "jnz_s"
120
    next_s <= fetch;
121
    
122
    when jz_s =>         --when current state is "jz_s"
123
    next_s <= fetch;
124
    
125
    when nop_s =>         --when current state is "nop_s"
126
    next_s <= fetch;
127
    
128
    when inc_s =>         --when current state is "inc_s"
129
    next_s <= wa;
130
    
131
    when dec_s =>         --when current state is "dec_s"
132
    next_s <= wa;
133
    
134
    when halt_s =>         --when current state is "halt_s"
135
    next_s <= halt_s;
136
137
    when rab =>       --when current state is "rab"
138
    if(input ="0000") then
139
    next_s <= add_s;
140
    elsif(input ="0001") then
141
    next_s <= sub_s;
142
    elsif(input ="0010") then
143
    next_s <= mov_ab_s;
144
    elsif(input ="0011") then
145
    next_s <= and_s;
146
    elsif(input ="0100") then
147
    next_s <= or_s;
148
    elsif(input ="1100") then
149
    next_s <= inc_s;
150
    elsif(input ="1101") then
151
    next_s <= dec_s;
152
    
153
    end if;
154
    
155
    when wa =>         --when current state is "wa"
156
    next_s <= fetch;
157
    
158
    when wb =>         --when current state is "wb"
159
    next_s <= fetch;
160
    
161
    when ra =>         --when current state is "wb"
162
    if(input ="0101") then
163
    next_s <= mov_ba_s;
164
    elsif(input ="0111") then
165
    next_s <= out_s;
166
    end if;
167
    
168
         
169
end case;
170
end process;
171
    
172
    output_logic:process(current_s)
173
    begin
174
        case current_s is
175
            
176
        when fetch=>
177
                pc_enable<='1';
178
                alu_enable<='0';
179
                rom_enable<='1';
180
                reg_enable<='0';
181
                ir_enable<='0';
182
                load_a<="UUU";
183
                load_b<="UUU";
184
                sel<='U';
185
                
186
        when decode=>
187
                pc_enable<='0';
188
                alu_enable<='0';
189
                rom_enable<='0';
190
                reg_enable<='0';
191
                ir_enable<='1';
192
                load_a<="UUU";
193
                load_b<="UUU";
194
                sel<='U';
195
                
196
          when add_s=>
197
                pc_enable<='0';
198
                alu_enable<='1';
199
                rom_enable<='0';
200
                reg_enable<='0';
201
                ir_enable<='0';
202
                load_a<="UUU";
203
                load_b<="UUU";
204
                sel<='U';
205
                output<="0000";
206
                
207
          when sub_s=>
208
                pc_enable<='0';
209
                alu_enable<='1';
210
                rom_enable<='0';
211
                reg_enable<='0';
212
                ir_enable<='0';
213
                load_a<="UUU";
214
                load_b<="UUU";
215
                sel<='U';
216
                output<="0001";
217
                
218
         when mov_ab_s=>
219
                pc_enable<='0';
220
                alu_enable<='1';
221
                rom_enable<='0';
222
                reg_enable<='0';
223
                ir_enable<='0';
224
                load_a<="110";
225
                load_b<="110";
226
                sel<='0';
227
                output<="0010";
228
                
229
        when and_s=>
230
                pc_enable<='0';
231
                alu_enable<='1';
232
                rom_enable<='0';
233
                reg_enable<='0';
234
                ir_enable<='0';
235
                load_a<="UUU";
236
                load_b<="UUU";
237
                sel<='U';
238
                output<="0011";
239
                
240
        when or_s=>
241
                pc_enable<='0';
242
                alu_enable<='1';
243
                rom_enable<='0';
244
                reg_enable<='0';
245
                ir_enable<='0';
246
                load_a<="UUU";
247
                load_b<="UUU";
248
                sel<='U';
249
                output<="0100";
250
                
251
        when mov_ba_s=>
252
                pc_enable<='0';
253
                alu_enable<='1';
254
                rom_enable<='0';
255
                reg_enable<='0';
256
                ir_enable<='0';
257
                load_a<="UUU";
258
                load_b<="UUU";
259
                sel<='U';
260
                output<="0101";
261
                
262
        when in_s=>
263
                pc_enable<='0';
264
                alu_enable<='0';
265
                rom_enable<='0';
266
                reg_enable<='1';
267
                ir_enable<='0';
268
                load_a<="110";
269
                load_b<="UUU";
270
                sel<='1'; 
271
                output<="0110";
272
                
273
        when out_s=>
274
                pc_enable<='0';
275
                alu_enable<='1';
276
                rom_enable<='0';
277
                reg_enable<='0';
278
                ir_enable<='0';
279
                load_a<="UUU";
280
                load_b<="UUU";
281
                sel<='0';
282
                output<="0111";
283
                
284
        when jmp_s=>
285
                pc_enable<='0';
286
                alu_enable<='0';
287
                rom_enable<='0';
288
                reg_enable<='0';
289
                ir_enable<='0';
290
                load_a<="UUU";
291
                load_b<="UUU";
292
                sel<='0';
293
                output<="1000";
294
                
295
        when jnz_s=>
296
                pc_enable<='0';
297
                alu_enable<='0';
298
                rom_enable<='0';
299
                reg_enable<='0';
300
                ir_enable<='0';
301
                load_a<="UUU";
302
                load_b<="UUU";
303
                sel<='0';
304
                output<="1001";
305
                
306
        when jz_s=>
307
                pc_enable<='0';
308
                alu_enable<='0';
309
                rom_enable<='0';
310
                reg_enable<='0';
311
                ir_enable<='0';
312
                load_a<="UUU";
313
                load_b<="UUU";
314
                sel<='0';
315
                output<="1010";
316
                
317
        when nop_s=>
318
                pc_enable<='0';
319
                alu_enable<='0';
320
                rom_enable<='0';
321
                reg_enable<='0';
322
                ir_enable<='0';
323
                load_a<="UUU";
324
                load_b<="UUU";
325
                sel<='0';
326
                output<="1011";
327
                
328
        when inc_s=>
329
                pc_enable<='0';
330
                alu_enable<='1';
331
                rom_enable<='0';
332
                reg_enable<='0';
333
                ir_enable<='0';
334
                load_a<="UUU";
335
                load_b<="UUU";
336
                sel<='U';
337
                output<="1100";
338
                
339
        when dec_s=>
340
                pc_enable<='0';
341
                alu_enable<='1';
342
                rom_enable<='0';
343
                reg_enable<='0';
344
                ir_enable<='0';
345
                load_a<="UUU";
346
                load_b<="UUU";
347
                sel<='U';
348
                output<="1101";
349
                
350
        when halt_s=>
351
                pc_enable<='0';
352
                alu_enable<='1';
353
                rom_enable<='0';
354
                reg_enable<='1';
355
                ir_enable<='0';
356
                load_a<="101";
357
                load_b<="UUU";
358
                sel<='U';
359
                output<="0111";
360
                
361
         when wa=>
362
                pc_enable<='0';
363
                alu_enable<='0';
364
                rom_enable<='0';
365
                reg_enable<='1';
366
                ir_enable<='0';
367
                load_a<="110";
368
                load_b<="UUU";
369
                sel<='0';
370
                
371
          when wb=>
372
                pc_enable<='0';
373
                alu_enable<='0';
374
                rom_enable<='0';
375
                reg_enable<='1';
376
                ir_enable<='0';
377
                load_a<="UUU";
378
                load_b<="110";
379
                sel<='U';
380
                
381
          when rab=>
382
                pc_enable<='0';
383
                alu_enable<='0';
384
                rom_enable<='0';
385
                reg_enable<='1';
386
                ir_enable<='0';
387
                load_a<="101";
388
                load_b<="101";
389
                sel<='0';
390
                
391
        when ra=>
392
                pc_enable<='0';
393
                alu_enable<='0';
394
                rom_enable<='0';
395
                reg_enable<='1';
396
                ir_enable<='0';
397
                load_a<="101";
398
                load_b<="UUU";
399
                sel<='U';
400
                                    
401
  end case;
402
end process;
403
404
end behavioral;

von Typo (Guest)


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1
    enter_r<=enter;
2
    if(enter_r='0' and enter='1') then
3
    next_s <= fetch;
4
    else
5
    next_s <= in_s;
6
    end if;

What do you expect this to do? As you described a strictly combinatorial 
process, the condition is constantly false.

This is'nt a matter for a total newbie I think. You shall consider basic 
VHDL first and try simple constructions using the principle before 
trying such things and get lost in overwhelmingly large texts.

By the way:
1. Please add such lengthy code as an attachment rather than literally 
as a part of the posts text.
2. You do not write programs in VHDL but describe structures Please 
consider this as it may be the very reason for using the construct which 
I cited above.

: Edited by Moderator
von vhdl n. (Company: none) (pranoy)


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Typo wrote:
> enter_r<=enter;
>     if(enter_r='0' and enter='1') then
>     next_s <= fetch;
>     else
>     next_s <= in_s;
>     end if;
>
> What do you expect this to do?


sir, i expect this to give a rising edge detection of the enter input.

Typo wrote:
> Please add such lengthy code as an attachment rather than literally
> as a part of the posts text.

i'll keep that in mind :)

von Typo (Guest)


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>Sir, ...

No need to be so formal here. Just call us be our nicks. :-)

> ... i expect this to give a rising edge detection of the enter input.

I thought so. But it seem i was a bit too laconic.
This:

>As you described a strictly combinatorial
>process, the condition is constantly false.

contained the hint.

If you are unsure if something is combinatorical or clocked have look at 
the implementation. How you may have a look at it depends on the 
software you use.

However, if enter is not clocked into a flip-flop the code is not proper 
for detecting edges.

von Today (Guest)


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As our "famous" VHDL-crack Lothar Miller seems not to be present I add a 
link to an edge detection here: 
http://www.lothar-miller.de/s9y/categories/18-Flankenerkennung

The text is in German but the code shall be comprehensible either.

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> i've edited my code and is posting it now.
Pls attach long VHDL code as *.vhd file!
Its also qouted in the box where you enter your text:
1
Rules — please read before posting
2
3
    Post long source code as attachment, not in the text


Typo wrote:
> not write programs in VHDL but describe structures ...
... or hardware behaviour.
But as the word itself says: VHDL is a hardware description language, 
not a hardware programming language.

vhdl newbie wrote:
> i've edited my code and is posting it now.
And ist this code ok in simulation? I assume not, because:
> process (current_s,enter,input,a_zero_status)
enter_r is missing in this sensitivity list.

> load_a <= "UUU";
> load_b <= "UUU";
Do you think the synthesizer can implement 'U' level in real hardware? 
Which voltage would one measure on a 'U' level?

: Edited by Moderator
von Typo (Guest)


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@ Lothar Miller
>... or hardware behaviour.
Grmbl. Let's have an in depth discussion about that matter. Someday. :-)

von vhdl n. (Company: none) (pranoy)


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Typo wrote:
> if enter is not clocked into a flip-flop the code is not proper
> for detecting edges.

i've changed my code now. (check line 39)
please check my code and see whether it is correct.

Lothar Miller wrote:
> And ist this code ok in simulation? I assume not

YES it is working in Modelsim simulation.

Lothar Miller wrote:
>> load_a <= "UUU";
>> load_b <= "UUU";
> Do you think the synthesizer can implement 'U' level in real hardware?
> Which voltage would one measure on a 'U' level?

when i synthesised it in xilinx, i changed U to Z.
this happened because i copied the code from Modelsim.
i've attached the new code.

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> Lothar Miller wrote:
>> And ist this code ok in simulation? I assume not
> YES it is working in Modelsim simulation.
Then you may have a different behaviour in reality, because the 
sensitivity list is for simulation only!

> when i synthesised it in xilinx, i changed U to Z.
You cannot have a 'Z' level inside nowadays FPGAs. Tristate levels are 
resolved with a multiplexer by the synthesizer.

> i've attached the new code.
enter_r is missing in this sensitivity list. I already mentioned this, 
didn't I?

> enter : in std_logic;
Where does this signal come from? Is it a asynchronous signal from 
outside the FPGA (eg. a key, switch)? If so, then you have to sync this 
signal to the 'clk' clock domain...

von vhdl n. (Company: none) (pranoy)


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Lothar Miller wrote:
> enter_r is missing in this sensitivity list.

done it now.

Lothar Miller wrote:
>> enter : in std_logic;
> Where does this signal come from? Is it a asynchronous signal from
> outside the FPGA (eg. a key, switch)?

YES, it is an async signal from outside (a dip switch or a push button).

Lothar Miller wrote:
> If so, then you have to sync this
> signal to the 'clk' clock domain.
1
begin
2
 if (reset='1') then
3
  current_s <= fetch;  --default state on reset.
4
  pc_reset<='1';
5
elsif (rising_edge(clk)) then
6
  current_s <= next_s;   --state change.
7
  
8
  enter_r<=enter;
9
  
10
  pc_reset<='0';
11
end if;
12
end process;

is this how to sync enter with the clock?

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> is this how to sync enter with the clock?
In that snippet enter is not synced up to now. To be in sync you must 
add (at least) one more flipflop stage. So it should look like   enter 
-> enter_s -> enter_r   and then enter_s and enter_r are used for edge 
detection. But the link for this was already posted...

What happens without synchronizing is shown there (try Google 
translate):
http://www.lothar-miller.de/s9y/archives/64-State-Machine-mit-asynchronem-Eingang.html

: Edited by Moderator
von vhdl n. (Company: none) (pranoy)


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did the sampling using a DFF.

but now there is a different problem.

if my program is

in a
mov b,a
in a
add a,b
halt.

i need the two in statements to read two different values.
but now when i give a '1' with dip switch then both my in instructions 
work simultaneously and i get the same input at both a and b registers.

my project guide said that it may be due to some sparking in the switch 
which causes multiple rising edges and as the FPGA is very fast both the 
instructions work at the same time.

please help me with this.

why is this happening?

is there any problem with my code?

pls suggest a method to overcome this.

thanks in advance.

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> is there any problem with my code?
Who knows? Post your VHDL file(s). Otherwise only guessing around is 
possible...

Also write some words about the hadrware: which FPGA? How are the 
switches connected? ...

And: usually you MUST begin a new thread for a new question. It is not 
good practice to take over someone others thread.

von vhdl n. (Company: none) (pranoy)


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Lothar Miller wrote:
> Post your VHDL file(s)

i've posted it previously.

posting it again :)


Lothar Miller wrote:
> which FPGA?

Spartan 3

Lothar Miller wrote:
> How are the
> switches connected?

the enter is connected to a dip switch on the FPGA board itself.

Lothar Miller wrote:
> It is not
> good practice to take over someone others thread.

this thread was started by me :)

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> Lothar Miller wrote:
>> It is not good practice to take over someone others thread.
> this thread was started by me :)
Hmmm, okokokokok... :-/

vhdl newbie wrote:
>   enter_r<=enter;
> end if;
> end process;
> is this how to sync enter with the clock?
Yes, but afterwards you should use the sync'ed enter in your 
description...

vhdl newbie wrote:
> but now when i give a '1' with dip switch then both my in instructions
> work simultaneously and i get the same input at both a and b registers.
You use a dip switch as the clock source?
That will never work unless its a bounce-free switch.

> my project guide said that it may be due to some sparking in the switch
> which causes multiple rising edges and as the FPGA is very fast both the
> instructions work at the same time.
It doesn't do it in the same time, but it does it within 50ns one after 
the other. For you this is looking like "the same time".

> is there any problem with my code?
Not more than already mentioned. Its a problem with your hardware now.

von vhdl n. (Company: none) (pranoy)


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Lothar Miller wrote:
> Its a problem with your hardware now.

will giving it to a debounce circuit work??

what will be the delay after which the switch reaches a stable state?

von Lothar M. (lkmiller) (Moderator)


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I don't know, because theres no answer to the question about the clock 
source: where does "clk" come from?

von vhdl n. (Company: none) (pranoy)


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Lothar Miller wrote:
>
> source: where does "clk" come from?

clock is FPGA clock (50MHz)

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> but now when i give a '1' with dip switch then both my in instructions
> work simultaneously and i get the same input at both a and b registers
And what is that "dip swith"? Is it connected to the "enter" signal?

von vhdl n. (Company: none) (pranoy)


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yes

enter is connected to the dip switch.

i got this code from the net for debouncing.

how can i get a clean 0 to 1 transition from this?
1
LIBRARY ieee;
2
USE ieee.std_logic_1164.all;
3
USE ieee.std_logic_unsigned.all;
4
5
ENTITY debounce IS
6
  GENERIC(
7
    counter_size  :  INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
8
  PORT(
9
    clk     : IN  STD_LOGIC;  --input clock
10
    button  : IN  STD_LOGIC;  --input signal to be debounced
11
    result  : OUT STD_LOGIC); --debounced signal
12
END debounce;
13
14
ARCHITECTURE logic OF debounce IS
15
  SIGNAL flipflops   : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
16
  SIGNAL counter_set : STD_LOGIC;                    --sync reset to zero
17
  SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
18
BEGIN
19
20
  counter_set <= flipflops(0) xor flipflops(1);   --determine when to start/reset counter
21
  
22
  PROCESS(clk)
23
  BEGIN
24
    IF(clk'EVENT and clk = '1') THEN
25
      flipflops(0) <= button;
26
      flipflops(1) <= flipflops(0);
27
      If(counter_set = '1') THEN                  --reset counter because input is changing
28
        counter_out <= (OTHERS => '0');
29
      ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
30
        counter_out <= counter_out + 1;
31
      ELSE                                        --stable input time is met
32
        result <= flipflops(1);
33
      END IF;    
34
    END IF;
35
  END PROCESS;
36
END logic;

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> i got this code from the net for debouncing.
Aha, the copy&paste generation...

> how can i get a clean 0 to 1 transition from this?
Why not thinking for yourself? I already posted the skeletons for this 
edge detection in http://embdev.net/topic/320582#3483355

Or at least copying from the right place?
http://www.lothar-miller.de/s9y/categories/18-Flankenerkennung

Ok, give me your hand and I will guide you through this mission 
impossible:
1
signal enter_r, enter_s :std_logic;
2
3
begin
4
5
process (clk,reset)
6
begin
7
 if (reset='1') then
8
  current_s <= fetch;  --default state on reset.
9
  pc_reset<='1';
10
elsif (rising_edge(clk)) then
11
  current_s <= next_s;   --state change.
12
  
13
  enter_r <=enter_s;
14
  enter_s <=enter;
15
  
16
  pc_reset<='0';
17
end if;
18
end process;
19
20
--state machine process.
21
process (current_s,enter_s,enter_r,input,a_zero_status)
22
begin
23
  case current_s is
24
    
25
    when fetch =>        --when current state is "fetch"
26
    next_s <= decode;
27
    :    
28
    when in_s =>         --when current state is "in_s"
29
    if enter_s='1' and enter_r='0' then -- rising edge
30
       next_s <= fetch;
31
    else
32
       next_s <= in_s;
33
    end if;
34
    :

von vhdl n. (Company: none) (pranoy)


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Lothar Miller wrote:
> Why not thinking for yourself? I already posted the skeletons for this
> edge detection in http://embdev.net/topic/320582#3483355

did some thinking and was gonna do like this

route the enter signal to the input of the debouncer module and take the 
output of this as the enter for my FSM.

OR

route the enter signal to the input of the debouncer module and take the 
output of this to DFF series and its output as the enter for my FSM
will my problems be solved??

asked that to see if anyone has a more clean idea. :)

Lothar Miller wrote:
> when in_s =>         --when current state is "in_s"
>     if enter_s='1' and enter_r='0' then -- rising edge
>        next_s <= fetch;

if the switch is bouncing, then will this work ?
i tried this and didn't work.

Lothar Miller wrote:
> Aha, the copy&paste generation...

as the input instruction was not working previously, i made some changes 
in my project and made the program memory and data memory into RAMs.

will start a new thread about this in the near future.


so, copying was the last resort :)

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> if the switch is bouncing, then will this work ?
No, you're right, it won't work. The 50MHz clock is too fast...

> so, copying was the last resort :)
The debouncing unit you found is a counter, that is reset, when the 
input changes. Otherwise it counts up and when it reaches a certain 
level the input is regarded as stable. Then the input signal is 
forwarded.

You could write this in a few lines in your code:
1
signal enter_r, enter_s :std_logic;
2
constant maxbounce : integer := 50000;
3
signal stablecnt : integer 0 to maxbounce ;
4
5
begin
6
7
process (clk,reset)
8
begin
9
 if (reset='1') then
10
  current_s <= fetch;  --default state on reset.
11
  pc_reset<='1';
12
elsif (rising_edge(clk)) then
13
  current_s <= next_s;   --state change.
14
  
15
  enter_r <=enter_s;
16
  enter_s <=enter;
17
  if enter_s/=enter_r then
18
     stablecnt <= 0;
19
  elsif stablecnt < maxbounce then
20
     stablecnt <= stablecnt+1;
21
  end if;
22
23
  pc_reset<='0';
24
end if;
25
end process;
26
27
--state machine process.
28
process (current_s,enter_s,stablecnt,input,a_zero_status)
29
begin
30
  case current_s is
31
    
32
    when fetch =>        --when current state is "fetch"
33
    next_s <= decode;
34
    :    
35
    when in_s =>         --when current state is "in_s"
36
    if stablecnt=maxbounce and enter_s='1' then -- debounced rising edge
37
       next_s <= fetch;
38
    else
39
       next_s <= in_s;
40
    end if;
41
    :

: Edited by Moderator
von vhdl n. (Company: none) (pranoy)


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i gave it a go.

It is working but there is a small problem.

before the program is executed, we should give an additional enter( so 
to input a data we now need 2 rising edges of enter instead of 1).

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> before the program is executed, we should give an additional enter( so
> to input a data we now need 2 rising edges of enter instead of 1).
No. Forget that whole "rising edge view". What you really need is one 
more state at the start of the whole thing. And to leave that state you 
check the switch in the same way as you do it now in the in_s state.

BTW: Did I already mention the word "thinking"?

von vhdl n. (Company: none) (pranoy)


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Lothar Miller wrote:
> BTW: Did I already mention the word "thinking"?

i did that, but i added an NOP state after the in_s state.

here i checked if the enter signal attains a zero back. :)

Lothar Miller wrote:
> And to leave that state you
> check the switch in the same way as you do it now in the in_s state.

i didn't understand this.

did you mean to check if enter is a 0 or 1?

von vhdl n. (Company: none) (pranoy)


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guys i'm posting my complete project files here.

if anyone can program a spartan3 with these files please check why u 
need 3 enter signals for entering 2 values.

the present program is

in a
mov b,a
in a
add a,b
halt

von Lothar M. (lkmiller) (Moderator)


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vhdl newbie wrote:
> if anyone can program a spartan3 with these files please check
Before programming the Almighty set the simulation. Which one of the 
files is the test bench? What result do you get when you are simualting 
your code?

>       if alu_enable='1' then
>          if (clock'event and clock='1') then
Where did you find this way to describe a clock enable?
Usually in the synthesis guidelines you will find it the other way 
round:
  if (clock'event and clock='1') then
     if alu_enable='1' then

von vhdl n. (Company: none) (pranoy)


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Lothar Miller wrote:
> Which one of the
> files is the test bench? What result do you get when you are simualting
> your code?

i think i have drifted away from the subject of this thread
so i'm starting a new thread.

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