library ieee; use ieee.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; enter : in std_logic; input:in std_logic_vector(3 downto 0); output:out std_logic_vector(3 downto 0); pc_enable: out std_logic; alu_enable: out std_logic; rom_enable: out std_logic; reg_enable: out std_logic; ir_enable: out std_logic; load_a:out std_logic_vector(2 downto 0); load_b:out std_logic_vector(2 downto 0); pc_reset:out std_logic; a_zero_status:in std_logic; sel: out std_logic; in_led:out std_logic ); end mealy; architecture behavioral of mealy is type state_type is (fetch,decode,zero,add_s,sub_s,mov_ab_s,and_s,or_s,mov_ba_s,in_s,out_s,jmp_s,jnz_s,jz_s,inc_s,dec_s,halt_s,rab,wa,wb,ra,nop_s); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= fetch; --default state on reset. pc_reset<='1'; elsif (rising_edge(clk)) then current_s <= next_s; --state change. pc_reset<='0'; end if; end process; --state machine process. process (current_s,enter,input,a_zero_status) begin case current_s is when fetch => --when current state is "fetch" next_s <= decode; in_led<='0'; when decode => --when current state is "decode" if(input ="0000") then next_s <= rab; elsif(input ="0001") then next_s <= rab; elsif(input ="0010") then next_s <= rab; elsif(input ="0011") then next_s <= rab; elsif(input ="0100") then next_s <= rab; elsif(input ="0101") then next_s <= ra; elsif(input ="0110") then next_s <= in_s; elsif(input ="0111") then next_s <= ra; elsif(input ="1000") then next_s <= jmp_s; elsif(input ="1001") then next_s <= jnz_s; elsif(input ="1010") then next_s <= jz_s; elsif(input ="1011") then next_s <= nop_s; elsif(input ="1100") then next_s <= rab; elsif(input ="1101") then next_s <= rab; elsif(input ="1111") then next_s <= halt_s; else next_s<=decode; end if; when add_s => --when current state is "add_s" next_s <= wa; when sub_s => --when current state is "sub_s" next_s <= wa; when mov_ab_s => --when current state is "mov_ab_s" next_s <= wa; when and_s => --when current state is "and_s" next_s <= wa; when or_s => --when current state is "or_s" next_s <= wa; when mov_ba_s => --when current state is "mov_ba_s" next_s <= wb; when in_s => --when current state is "in_s" if(enter='1') then next_s <= zero; in_led<='0'; else next_s <= in_s; in_led<='1'; end if; when out_s => --when current state is "out_s" next_s <= fetch; when jmp_s => --when current state is "jmp_s" next_s <= fetch; when jnz_s => --when current state is "jnz_s" next_s <= fetch; when jz_s => --when current state is "jz_s" next_s <= fetch; when nop_s => --when current state is "nop_s" next_s <= fetch; when inc_s => --when current state is "inc_s" next_s <= wa; when dec_s => --when current state is "dec_s" next_s <= wa; when halt_s => --when current state is "halt_s" next_s <= halt_s; when rab => --when current state is "rab" if(input ="0000") then next_s <= add_s; elsif(input ="0001") then next_s <= sub_s; elsif(input ="0010") then next_s <= mov_ab_s; elsif(input ="0011") then next_s <= and_s; elsif(input ="0100") then next_s <= or_s; elsif(input ="1100") then next_s <= inc_s; elsif(input ="1101") then next_s <= dec_s; end if; when wa => --when current state is "wa" next_s <= fetch; when wb => --when current state is "wb" next_s <= fetch; when ra => --when current state is "wb" if(input ="0101") then next_s <= mov_ba_s; elsif(input ="0111") then next_s <= out_s; end if; when zero=> if(enter='0') then next_s<=fetch; else next_s<=zero; end if; end case; end process; output_logic:process(current_s) begin case current_s is when fetch=> pc_enable<='1'; alu_enable<='0'; rom_enable<='1'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; when decode=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='0'; ir_enable<='1'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; when add_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; output<="0000"; when sub_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; output<="0001"; when mov_ab_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="110"; load_b<="110"; sel<='0'; output<="0010"; when and_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; output<="0011"; when or_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; output<="0100"; when mov_ba_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; output<="0101"; when in_s=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='1'; ir_enable<='0'; load_a<="110"; load_b<="ZZZ"; sel<='1'; output<="0110"; when out_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='0'; output<="0111"; when jmp_s=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='0'; output<="1000"; when jnz_s=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='0'; output<="1001"; when jz_s=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='0'; output<="1010"; when nop_s=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='0'; output<="1011"; when inc_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; output<="1100"; when dec_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; output<="1101"; when halt_s=> pc_enable<='0'; alu_enable<='1'; rom_enable<='0'; reg_enable<='1'; ir_enable<='0'; load_a<="101"; load_b<="ZZZ"; sel<='Z'; output<="0111"; when wa=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='1'; ir_enable<='0'; load_a<="110"; load_b<="ZZZ"; sel<='0'; when wb=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='1'; ir_enable<='0'; load_a<="ZZZ"; load_b<="110"; sel<='Z'; when rab=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='1'; ir_enable<='0'; load_a<="101"; load_b<="101"; sel<='0'; when ra=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='1'; ir_enable<='0'; load_a<="101"; load_b<="ZZZ"; sel<='Z'; when zero=> pc_enable<='0'; alu_enable<='0'; rom_enable<='0'; reg_enable<='0'; ir_enable<='0'; load_a<="ZZZ"; load_b<="ZZZ"; sel<='Z'; end case; end process; end behavioral;