library ieee; use ieee.std_logic_1164.all; entity top_fsm is port( clock:in std_logic; D1:in std_logic_vector(7 downto 0); output:out std_logic_vector(7 downto 0); reset : in std_logic; in_led:out std_logic; enter : in std_logic ); end top_fsm; architecture arch of top_fsm is signal pc_enable_signal:std_logic; signal ir_enable_signal:std_logic; signal rom_enable_signal:std_logic; signal alu_enable_signal:std_logic; signal reg_enable_signal:std_logic; signal load_a_signal:std_logic_vector(2 downto 0); signal load_b_signal:std_logic_vector(2 downto 0); signal sel_signal:std_logic; signal reset_signal:std_logic; signal control_signal_from_rom:std_logic_vector(3 downto 0); signal control_signal_to_alu:std_logic_vector(3 downto 0); signal chumma:std_logic_vector(3 downto 0); signal dout_signal:std_logic_vector(7 downto 0); signal a_zero_status_signal:std_logic; signal enter_signal:std_logic; signal enter_signal1:std_logic; component edge_detect port (async_sig : in std_logic; clk : in std_logic; rise : out std_logic ); end component; component datapath_latest port( D1:in std_logic_vector(7 downto 0); a_zero_status:out std_logic; Dout:out std_logic_vector(7 downto 0); control:in std_logic_vector(3 downto 0); clock:in std_logic; alu_enable:in std_logic; reg_enable:in std_logic; sel:in std_logic; load_a:in std_logic_vector(2 downto 0); load_b:in std_logic_vector(2 downto 0) ); end component; component pc_rom_ent port(clock:in std_logic; pc_enable:in std_logic; rom_enable:in std_logic; pc_reset:in std_logic; ir_enable:in std_logic; opcode:out std_logic_vector(3 downto 0); a_zero_status:in std_logic ); end component; component debounce PORT( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END component; component mealy port (clk : in std_logic; reset : in std_logic; enter : in std_logic; input:in std_logic_vector(3 downto 0); output:out std_logic_vector(3 downto 0); pc_enable: out std_logic; alu_enable: out std_logic; rom_enable: out std_logic; reg_enable: out std_logic; ir_enable: out std_logic; load_a:out std_logic_vector(2 downto 0); load_b:out std_logic_vector(2 downto 0); pc_reset:out std_logic; a_zero_status:in std_logic; sel: out std_logic; in_led:out std_logic ); end component; begin deb:debounce port map( clk=>clock, button=>enter, result=>enter_signal ); edge:edge_detect port map( clk=>clock, async_sig=>enter_signal, rise=>enter_signal1 ); mem:pc_rom_ent port map( clock=>clock, pc_enable=>pc_enable_signal, rom_enable=>rom_enable_signal, ir_enable=>ir_enable_signal, pc_reset=>reset_signal, opcode=>control_signal_from_rom, a_zero_status=>a_zero_status_signal ); data:datapath_latest port map( D1=>D1, Dout=>output, control=>control_signal_to_alu, clock=>clock, sel=>sel_signal, alu_enable=>alu_enable_signal, reg_enable=>reg_enable_signal, load_a=>load_a_signal, load_b=>load_b_signal, a_zero_status=>a_zero_status_signal ); fsm:mealy port map( clk=>clock, reset=>reset, enter=>enter_signal1, input=>control_signal_from_rom, output=>control_signal_to_alu, pc_enable=>pc_enable_signal, ir_enable=>ir_enable_signal, rom_enable=>rom_enable_signal, alu_enable=>alu_enable_signal, reg_enable=>reg_enable_signal, load_a=>load_a_signal, load_b=>load_b_signal, pc_reset=>reset_signal, sel=>sel_signal, a_zero_status=>a_zero_status_signal, in_led=>in_led ); end arch;