library ieee; use ieee.std_logic_1164.all; entity pc_rom_ent is port(clock:in std_logic; pc_enable:in std_logic; rom_enable:in std_logic; ir_enable:in std_logic; pc_reset:in std_logic; a_zero_status:in std_logic; opcode:out std_logic_vector(3 downto 0) ); end pc_rom_ent; architecture pc_rom_arch of pc_rom_ent is signal pc_out:std_logic_vector(3 downto 0); signal opcode_signal:std_logic_vector(3 downto 0); signal address_signal:std_logic_vector(3 downto 0); signal rom_out:std_logic_vector(7 downto 0); component programcounter port(clock:in std_logic; pc_enable:in std_logic; pc_reset:in std_logic; input:in std_logic_vector(3 downto 0); opcode:in std_logic_vector(3 downto 0); output:out std_logic_vector(3 downto 0); a_zero_status:in std_logic ); end component; component rom port(addr:in std_logic_vector(3 downto 0); clock:in std_logic; rom_enable:in std_logic; dout:out std_logic_vector(7 downto 0) ); end component; component instruction_register port(data_in:in std_logic_vector(7 downto 0); clock:in std_logic; ir_enable:in std_logic; data_out:out std_logic_vector(7 downto 0)); end component; begin opcode<=opcode_signal; ir:instruction_register port map( data_in=> rom_out, clock=>clock, ir_enable=>ir_enable, data_out(7 downto 4)=>opcode_signal, data_out(3 downto 0)=>address_signal ); pc:programcounter port map( clock=>clock, pc_enable=>pc_enable, pc_reset=>pc_reset, input=>address_signal, opcode=>opcode_signal, output=>pc_out, a_zero_status=>a_zero_status ); mem:rom port map( addr=>pc_out, clock=>clock, rom_enable=>rom_enable, dout=>rom_out ); end pc_rom_arch;