Search results for "111"

Article

when "001" => aluout <= srca or srcb; when "010"|"110" => aluout <= sum; when "111" => aluout <= (0 => sum(31), others => '0'); when others => aluout <= (others => 'X'); end case; end process; zero <= '1' when (aluout = X"00000000") else '0'; dataadr <=

FPGA, VHDL & Verilog ·Chris Regform ·2015-04-13 02:17 ·5 Replies

File

main.txt

f4 brcc .+4 ; 0xf8 <__stack+0x19> f4: b8 01 movw r22, r16 f6: 7c c0 rjmp .+248 ; 0x1f0 <__stack+0x111> f8: 8a 85 ldd r24, Y+10 ; 0x0a fa: 9a 89 ldd r25, Y+18 ; 0x12 fc: 89 27 eor r24, r25 fe: 8a 87 std Y+10, r24 ; 0x0a 100: 24 30 cpi r18, 0x04 ; 4 102: 11 f0 breq .+4 ; 0x108 <__stack+0x29> 104: 22 30

in „flash-Fehler mit ATtiny2313, compile ok“ · Mikrocontroller und Digitale Elektronik · 2015-03-29 15:57

Article

Frequenzumrichter mit Raumzeigermodulation

Man spricht von den sechs Spannungsvektoren oder Raumzeigern. Hinzu kommen noch die Muster 000 und 111 bei welchen die Motorspannung 0V ist, da alle Wicklungen an + Udc oder - Udc hängen (Nullspannungsvektor). Gibt man nun die Ausgangsmuster 1 bis 6 mit der entsprechenden Frequenz heraus, bekommt man

Endvektor Nullspannungsvektor Nullspannungsvektor Endvektor Anfangsvektor Nullspannungsvektor 000 010 110 111 111 110 010 000 Werden anstelle eines Motors drei im Dreieck geschaltete Widerstände angeschlossen erhält man folgenden Spannungsverlauf: Es ist zu erkennen, wie der Anteil der positiven Spannungsanteile

Article ·2015-03-23 10:06

Thread

SDRAM Memory Controller for Terasic DE0-nano

s_init_pre; n.address(10) <= '1'; end if; -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then n.state <= s_init_ref;

FPGA, VHDL & Verilog ·jeorges FrenchRivera ·2015-03-20 14:19 ·6 Replies

File

TX.vhd

9600-- 2600 when "100", -- 19200-- 1300 when "101", -- 38400-- 866 when "110", -- 57600-- 432 when "111", --115200-- --108 when "111", -- 460800 --54 when "111", -- 921600 5200 when others; TX_proc: process(Clk) begin if(Clk'EVENT and Clk = '1') then --txstart <= START; IF (TX_FLG = '0' and START = '1

in „UART interface on FPGA“ · FPGA, VHDL & Verilog · 2015-03-02 19:53

Thread

VERILOG CODE

output reg match; reg [2:0] mem[7:0]; initial begin mem[0]=3'b110; mem[1]=3'b010; mem[2]=3'b111; mem[3]=3'b000; mem[4]=3'b110; mem[5]=3'b101; mem[6]=3'b011; mem[7]=3'b110; end always@(posedge clk) begin for(i=3'd0;i<8;i=i+1) begin if (in[i]==1'b1) sum=sum ^ mem[i]; end $display

FPGA, VHDL & Verilog ·Akshay E. ·2015-02-06 15:41 ·4 Replies

File

code1.vhdl.txt

byte_sub Port map (cypher1(119 downto 112),gclock,rst,e1,e2,data2); A3 : byte_sub Port map (cypher1(111 downto 104),gclock,rst,e1,e2,data3); A4 : byte_sub Port map (cypher1(103 downto 96),gclock,rst,e1,e2,data4); A5 : byte_sub Port map (cypher1(95 downto 88),gclock,rst,e1,e2,data5); A6 : byte_sub Port

in „VHDL coding Question“ · FPGA, VHDL & Verilog · 2014-11-27 06:47

File

full.vhdl.txt

:= SBOX_LOOKUP(state(127 downto 120)); b(119 downto 112) := SBOX_LOOKUP(state(119 downto 112)); b(111 downto 104) := SBOX_LOOKUP(state(111 downto 104)); b(103 downto 96) := SBOX_LOOKUP(state(103 downto 96)); b(95 downto 88) := SBOX_LOOKUP(state(95 downto 88)); b(87 downto 80) := SBOX_LOOKUP(state(87

in „VHDL coding Question“ · FPGA, VHDL & Verilog · 2014-11-27 06:46

File

code.v

byte_sub Port map (cypher1(119 downto 112),gclock,rst,e1,e2,data2); A3 : byte_sub Port map (cypher1(111 downto 104),gclock,rst,e1,e2,data3); A4 : byte_sub Port map (cypher1(103 downto 96),gclock,rst,e1,e2,data4); A5 : byte_sub Port map (cypher1(95 downto 88),gclock,rst,e1,e2,data5); A6 : byte_sub Port

in „VHDL coding Question“ · FPGA, VHDL & Verilog · 2014-11-26 20:00

Thread

Syntax Help with Project

"001" => tempLED <="011"; when "010" => tempLED <="000"; when "011" => tempLED <="111"; when others => tempLED <= "000"; end case; end if; end process; led_out <= tempLED; end balls_arch; library IEEE; use ieee.std_logic_1164.all; entity Baseball

"001" => tempLED <="011"; when "010" => tempLED <="000"; when "011" => tempLED <="111"; when others => tempLED <= "000"; end case; end if; end process; led_out <= tempLED; end ball_arch; library IEEE; use ieee.std_logic_1164.all; entity

FPGA, VHDL & Verilog ·Annon ·2014-11-27 04:37 ·2 Replies

File

img.txt

148 148 147 146 145 148 146 145 146 146 144 143 144 143 142 142 142 142 141 137 137 133 133 134 133 111 88 85 82 82 83 81 80 83 82 80 79 77 79 78 77 77 77 76 74 73 73 74 74 75 76 75 74 72 72 72 72 72 75 76 71 69 69 70 73 75 75 74 74 72 65 66 64 55 51 47 47 45 43 46 44 44 42 40 38 38 40 44 42 39 39 40

in „help in reading a large text file using verilog.“ · FPGA, VHDL & Verilog · 2014-11-26 06:13

Article

Receiver-Mainboard Plattform Philips PNX8950

ihrer Größe mit TFTP statt mit kermit zu kopieren. Laden des Kernels Mittels TFTP: tftp $(loadaddr) 111.222.333.444:uImage Mittels kermit: loadb $(loadaddr) Flashen des Kernels: Mit "connect" auf die Box wechseln mtdparts default nand erase.part Linux nand write $(loadaddr) Linux $(filesize) Kernel booten

Article ·2014-11-05 15:58

PDF

DUE_Faradays_law.pdf

1878,1979,2081,2171,2273,2364,2465,2550,2647,2753 };//voltage U double[] Frq_f = { 27.99,55.98,83.91,111.92,139.74,167.76,195.5,223.71,251.26,279.33 };//frequency public void draw_fct(Graphics g, TFkt_00 z, Color c) { double x, dx; int xvon, yvon, xbis, ybis; Pen pen = new Pen(c, 1); dx = (xmax - xmin)

in „Arduino Due in plain C“ · Mikrocontroller und Digitale Elektronik · 2014-11-02 11:10

File

main.lst

----------------------------- 109 ; Function stop_cpu 110 ; --------------------------------- 0000 111 _stop_cpu_start:: 0000 112 _stop_cpu: 113 ;driver.c:10: __endasm ; 0000 76 [ 4] 114 halt 115 ;driver.c:12: while (1); 0001 116 00102$: 0001 18 FE [12] 117 jr 00102$ 0003 118 _stop_cpu_end:: 119 ;driver.c

in „Mehrdimensionale char-arrays“ · Mikrocontroller und Digitale Elektronik · 2014-10-22 13:55

Thread

Display 640x480 Nexys 3 board

--------------------------------------- if hcounter < 640 and vcounter < 480 then red<= "111"; green<="111"; blue<="11"; hsync<='1'; vsync<='0'; else red<= "111"; green<="111"; blue<="11"; hsync<='1'; vsync<='0'; end if; ----------

FPGA, VHDL & Verilog ·sketchy ·2014-10-15 18:57 ·8 Replies

PDF

ADXL362.pdf

the HALF_BW bit setting. 000 12.5 Hz 001 25 Hz 010 50 Hz 011 100 Hz (reset default) 100 200 Hz 101…111 400 Hz Rev. B | Page 33 of 44 ADXL362 Data Sheet POWER CONTROL REGISTER Address: 0x2D, Reset: 0x00, Name: POWER_CTL Table 18. Bit Descriptions for POWER_CTL Bits BitName Settings Description Reset Access

in „Hilfe bei Erstellung einer Library für den ADXL362“ · Mikrocontroller und Digitale Elektronik · 2014-07-25 09:16

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problem with sinulation in ISE (FPGA)

VHDL coding itself in each entity. The PN generator for Source 1 is initialized with (S2 S1 S0) = 111 and generates PN code 1110100 whereas the PN generator for Source 2 is initialized with (S2 S1 S0) = 110 and generates PN code1101001. so I wrote the sketch I create two inputs one is( CLOCK )

FPGA, VHDL & Verilog ·Zakariya AL-Mazroo'Ee ·2014-06-28 10:00 ·2 Replies

Thread

RAM overflow is it acceptable

: 32801 from 26624 -------> 123% Number of 4 input LUTs : 29767 from 26624 -------> 111% Number of bonded IOBs : 33 from 221 -------> 14% Number of GCLKs : 2 from 8 ------->25% ------------------------------------------------------------

FPGA, VHDL & Verilog ·Abdallah ·2014-04-17 16:26 ·4 Replies

File

error_xc8.txt

%f:%%l: advisory: (%%n) %%s" -obuild/default/production/main_tmp.p1 main_tmp.c cFL.h:77: warning: (111) redefining preprocessor macro "__delay_us" (C:\Program Files (x86)\Microchip\xc8\v1.20\include\pic18.h: 150) cFL.h:78: warning: (111) redefining preprocessor macro "__delay_ms" (C:\Program Files (x86)\Microchip\xc8\v1.20\include\pic18.h: 151) cFL.h:92: warning: (111) redefining preprocessor macro "__EEPROM_DATA" (C:\Program Files (x86)\Microchip\xc8\v1.20\include\pic18.h: 63) (908) exit status = 1 make[2]: *** [build/default/production/main_tmp.p1] Error 1 make

in „Erklärung für Macrodefinition wird benötigt“ · Mikrocontroller und Digitale Elektronik · 2014-03-18 14:48

File

debug_okay.asm

ori r24, 0x02 ; 2 144: 80 83 st Z, r24 TIMSK1 |= (1<<ICIE1) | (1<<TOIE1); 146: ef e6 ldi r30, 0x6F ; 111 148: f0 e0 ldi r31, 0x00 ; 0 14a: 80 81 ld r24, Z 14c: 81 62 ori r24, 0x21 ; 33 14e: 80 83 st Z, r24 cli(); // §§§ muss spätestens vor dem letzten Befehl stehen, dieser ist allerdings beliebig (setting

in „Fehler bei einfacher Integer-Division?“ · Mikrocontroller und Digitale Elektronik · 2014-02-01 22:04

File

debug_error.asm

ori r24, 0x02 ; 2 144: 80 83 st Z, r24 TIMSK1 |= (1<<ICIE1) | (1<<TOIE1); 146: ef e6 ldi r30, 0x6F ; 111 148: f0 e0 ldi r31, 0x00 ; 0 14a: 80 81 ld r24, Z 14c: 81 62 ori r24, 0x21 ; 33 14e: 80 83 st Z, r24 cli(); // §§§ muss spätestens vor dem letzten Befehl stehen, dieser ist allerdings beliebig (setting

in „Fehler bei einfacher Integer-Division?“ · Mikrocontroller und Digitale Elektronik · 2014-02-01 22:03

Thread

does vhdl accept this assignment of bits

first_part[/vhdl] contains the copied bits from the stream, signal flag contain the actual no bits, either 111 for 001 or 11 for 01 and [vhdl]signal second_part[/vhdl] contains the final inverted form. Here, i want to ask that if the do the following, would it achieve my purpose without error: [vhdl] first_part

FPGA, VHDL & Verilog ·Amna Khan ·2014-01-06 21:53 ·3 Replies

Article

LPC1xxx für Umsteiger

sehr zu empfehlen. = Sonstige Informationen = Spannungsversorgung 1,8 bis 3,3V DIL Gehäuse: den LPC111xFD gibt es relativ neu auch im DIL-28 Gehäuse, Bezugsquellen werden asap hier genannt, sobald verfügbar. Ein Programmieradapter ist bereits im Kit enthalten. Achtung: über den gleichen Adapter kann

Article ·2014-01-05 11:09

Thread

Counter in verilog

pulse it is 101 then output should be as follows: counter1 000,001,010,011,100,101,110,111, 000,001,.. counter2 011,100,101,110,111,000,001,010, 101,110,.. The code which I tried for that is as follows but not got the correct result ,so please help me to find out the mistake

FPGA, VHDL & Verilog ·Nisarg Shah ·2013-12-27 09:42 ·0 Replies

Thread

need help to modify my code

data = 8'b11100011; 7'b101: data = 8'b00110011; 7'b110: data = 8'b11110111; 7'b111: data = 8'b00111011; 7'b1000: data = 8'b00110001; 7'b1001: data = 8'b00010000; 7'b1010: data = 8'b00100000; 7'b1011: data = 8'b11101101; 7'b1100: data = 8'

= 8'b11110011; 7'b101: weight = 8'b11100110; 7'b110: weight = 8'b11101100; 7'b111: weight = 8'b11110110; 7'b1000: weight = 8'b11111001; 7'b1001: weight = 8'b00000010; 7'b1010: weight = 8'b11111011; 7'b1011: weight = 8'b00001100; 7'b1100:

FPGA, VHDL & Verilog ·shreyas patel ·2013-12-25 11:44 ·0 Replies

File

CRC.o.lst

text._ZN6TZApp4CCrc9Crc32FastEmm,"ax",%progbits 109 .align 2 110 .global _ZN6TZApp4CCrc9Crc32FastEmm 111 .thumb 112 .thumb_func 114 _ZN6TZApp4CCrc9Crc32FastEmm: 115 .LFB134: 44:../CRC.cpp **** /** Berechnet die Checksumme für einen einzelnen 32-bit Wert (Hardware-CRC) 45:../CRC.cpp **** * 46:../CRC.cpp

in „Problem mit GCC-Optimierung“ · Mikrocontroller und Digitale Elektronik · 2013-12-02 16:43

PDF

Datasheet_ATmega1281_doc2549.pdf

CKSEL3:1 and C2 (pF) 0.4 - 0.9 100 (2) – 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 8.0 - 16.04) 111 12 - 22 Notes: 1. This is the recommended CKSEL settings for the different frequency ranges. 2. This option should not be used with crystals, only with ceramic resonators. 3. If 8 MHz frequency exceeds

in „LM73 über TWI/I2C mit Atmega1281 auslesen“ · Mikrocontroller und Digitale Elektronik · 2013-09-24 14:55

Thread

Error in VHDL

when "00100000"=> y<="101"; when "01000000"=> y<="110"; when others=> y<="111"; end case; else y<="UUU"; end if; end process; end enc_arc; [/vhdl] this is my code but i get this error message

FPGA, VHDL & Verilog ·vhdl newbie ·2013-09-10 15:05 ·2 Replies

PDF

t6_1.pdf

014D5, D2367, DD0123, D4567, D ,D 100 101 α 000 001 Figure 6: First pass of top down heuristic. 110 111 010 011 along S and recursively calls itselfon each of the sub- 2 trees ro oted at M and M .The recursion terminates 1 2 when there are just two data signals remaining. Figure 4: Bo olean cub e corresp

in „Low power multiplexer design“ · FPGA, VHDL & Verilog · 2013-07-22 11:04

File

foo.dwarf-3.txt

uleb128 0x1 .long .LASF109 .byte 0x5 .uleb128 0x1 .long .LASF110 .byte 0x5 .uleb128 0x1 .long .LASF111 .byte 0x5 .uleb128 0x1 .long .LASF112 .byte 0x5 .uleb128 0x1 .long .LASF113 .byte 0x5 .uleb128 0x1 .long .LASF114 .byte 0x5 .uleb128 0x1 .long .LASF115 .byte 0x5 .uleb128 0x1 .long .LASF116 .byte 0x5

in „Simple C Frage zum Typ enum“ · Mikrocontroller und Digitale Elektronik · 2013-07-18 21:50

File

testmux.vhd

Tsel <= "100"; wait for 10 ns; Tsel <= "101"; wait for 10 ns; Tsel <= "110"; wait for 10 ns; Tsel <= "111"; wait for 10 ns; end process; end architecture behavioral;

in „to_unsigned()“ · FPGA, VHDL & Verilog · 2013-07-15 12:53

File

TB.txt

Tsel <= "100"; wait for 10 ns; Tsel <= "101"; wait for 10 ns; Tsel <= "110"; wait for 10 ns; Tsel <= "111"; wait for 10 ns; end process; end architecture behavioral;

in „to_unsigned()“ · FPGA, VHDL & Verilog · 2013-07-15 12:07

File

tinymips.v

logical and (for and) 6'b100101: alucont <= 3'b001; // logical or (for or) 6'b101010: alucont <= 3'b111; // set on less (for slt) default: alucont <= 3'b101; // should never happen endcase endcase endmodule // Datapath, including register file, ALU, muxes, and other registers module datapath #(parameter

in „help me..newbie in this language“ · FPGA, VHDL & Verilog · 2013-06-20 18:54

Thread

Verilog VGA code HS VS timing

vc >34 && vc < 515) begin if (hc > 143 && hc < 700) begin red = 3'b111; green = 3'b000; blue= 2'b00; end end end endmodule Plus , ucf file: CE: Start of Constraints generated by PACE #PACE: Start of PACE I/O

vc >34 && vc < 515) > begin > if (hc > 143 && hc < 700) > begin > red = 3'b111; > green = 3'b000; > blue= 2'b00; > end [code] else red = ... else red = [/code]

FPGA, VHDL & Verilog ·Keny Joneyer ·2016-01-06 17:48 ·7 Replies

Thread

compilation error

Error: ex4.vhd(89): Nonresolved signal 'sel_mux' has multiple sources. # Drivers: # ex4.vhd(111):Statement MUX_DFF # ex4.vhd(96):Conditional signal assignment line__96 # ** Error: ex4.vhd(139): VHDL Compiler exiting # D:/Modeltech_pe_edu_10.2a/win32pe_edu/vcom failed. thanks in advance

FPGA, VHDL & Verilog ·amitai ·2013-05-16 07:24 ·5 Replies

File

Fehlermeldungen.txt

`mymac' stack.o:C:\Dokumente und Einstellungen\erster\Eigene Dateien\ETH_M32EX\default/../stack.c:111: more undefined references to `mymac' follow stack.o: In function `stack_init': C:\Dokumente und Einstellungen\erster\Eigene Dateien\ETH_M32EX\default/../stack.c:115: undefined reference to `enc_init

in „GCC: wie kompiliere ich ETH_M32EX von Ulrich Radig richtig?“ · Mikrocontroller und Digitale Elektronik · 2013-05-08 06:17

Thread

Header for PIC16F688 with C-Compiler

digital pin. I don't see it on this chip. As for the configuration bits (what is set in MPLAB, page 111 of datasheet), make sure the watchdog is disabled for now, WDTE, and set FOSC to binary 100. That sets it to use the internal oscillator. Make sure the MCLR pin is pulled to +5 so it doesn't get stuck

µC & Digital Electronics ·Stefan Hölfer ·2013-05-08 17:33 ·3 Replies

Article

Elektronischer Zauberwuerfel

geschaltet werden muss. Ausgabe der SPI-Daten zum Schalten der LEDs Download der Sourcen Sourcen Rev.111 PC-Software. Die PC-Software dient nur zur Kontrolle und Simulation des elektronischen Würfels. Es können Drehbewegungen an den realen Würfel gesendet werden, die dieser dann ausführt und seine aktualisierten

Article ·2013-04-11 16:31

Article

DockstarDebianSqueeze

einstellung (Beispieladressen) : /etc/network/interfaces iface eth0 inet static address 192.168.0.111 netmask 255.255.255.0 network 192.168.0.0 broadcast 192.168.0.255 gateway 192.168.0.1 Einen einfachen kleinen Texteditor installieren: dockstar $ apt-get install nano Nur für USB-Sticks: Nun die Verzeichnisse

Article ·2013-02-18 23:06

File

lcd.c

, 89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115, 90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116, 91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117, 92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118, 93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119, 94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120

in „Programm startet neu bei Zugriff auf array“ · Mikrocontroller und Digitale Elektronik · 2013-02-05 21:07

Thread

Help with VHDL code

ELSIF FO = 101 THEN SOUT <= -BI; ELSIF FO = 110 THEN SOUT <= AI + 1; ELSIF FO = 111 THEN SOUT <= AI - 1; END IF; END PROCESS; END FUNCTION8; I guess what Im really asking is do you see anything wrong with the code?? where did I go wrong?? Any suggestions on some

FPGA, VHDL & Verilog ·Eddie Pena ·2013-01-29 18:30 ·9 Replies

Thread

coding the vga port

- 803 = Sync-pulse + Back-porch + Visible-area then if bin = '1' then red_out <= "111"; green_out <= "111"; blue_out <= "11"; elsif bin = '0' then red_out <= "000"; green_out <= "000"; blue_out <= "00"; end if; else red_out <

FPGA, VHDL & Verilog ·keith dunc ·2013-02-12 08:12 ·6 Replies

Thread

error (12007) top-level design entity "projet" is undefined

111

FPGA, VHDL & Verilog ·Lpsyco Lpsyco ·2022-07-27 16:28 ·5 Replies

Thread

car taillights

left2on : std_logic_vector(3 downto 1) := "011"; CONSTANT left3on : std_logic_vector(3 downto 1) := "111"; CONSTANT rightoff : std_logic_vector(3 downto 1) := "000"; CONSTANT right1on : std_logic_vector(3 downto 1) := "100"; CONSTANT right2on : std_logic_vector(3 downto 1) := "110"; CONSTANT right3on : std_logic_vector(3 downto 1) := "111"; signal sclk: std_logic; BEGIN DIVIDER : entity work.clock_divider(behavior) generic map (DIVISOR => DIVISOR) port map (clk => clk, rst => rst, q => sclk); clocked : PROCESS(sclk,rst

FPGA, VHDL & Verilog ·Dfd D. ·2019-12-04 18:11 ·2 Replies

Article

SportTracker

LED Output: Sign of Life (Blinkende LED) 98 PC8 SDIO Micro SD Card: D0 99 PC9 SDIO Micro SD Card: D1 111 PC10 SDIO Micro SD Card: D2 112 PC11 SDIO Micro SD Card: D3 113 PC12 SDIO Micro SD Card: CLK 7 PC13 GPIO Taster Input: Lap/Reset 116 PD2 SDIO Micro SD Card: CMD 117 PD3 GPIO Joystick Input: Down 92

Article ·2012-09-09 12:22

Search results for "111"

216 results for 111 Search results for "111"

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