HA_Sensor_Raumklima.elf:     file format elf32-avr


Disassembly of section .text:

00000000 <__vectors>:
   0:	0c 94 34 00 	jmp	0x68	; 0x68 <__ctors_end>
   4:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
   8:	0c 94 47 02 	jmp	0x48e	; 0x48e <__vector_2>
   c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  10:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  14:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  18:	0c 94 5e 00 	jmp	0xbc	; 0xbc <__vector_6>
  1c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  20:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  24:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  28:	0c 94 68 00 	jmp	0xd0	; 0xd0 <__vector_10>
  2c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  30:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  34:	0c 94 87 00 	jmp	0x10e	; 0x10e <__vector_13>
  38:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  3c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  40:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  44:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  48:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  4c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  50:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  54:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  58:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  5c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  60:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  64:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>

00000068 <__ctors_end>:
  68:	11 24       	eor	r1, r1
  6a:	1f be       	out	0x3f, r1	; 63
  6c:	cf ef       	ldi	r28, 0xFF	; 255
  6e:	d4 e0       	ldi	r29, 0x04	; 4
  70:	de bf       	out	0x3e, r29	; 62
  72:	cd bf       	out	0x3d, r28	; 61

00000074 <__do_copy_data>:
  74:	11 e0       	ldi	r17, 0x01	; 1
  76:	a0 e0       	ldi	r26, 0x00	; 0
  78:	b1 e0       	ldi	r27, 0x01	; 1
  7a:	ec e8       	ldi	r30, 0x8C	; 140
  7c:	fc e0       	ldi	r31, 0x0C	; 12
  7e:	02 c0       	rjmp	.+4      	; 0x84 <__do_copy_data+0x10>
  80:	05 90       	lpm	r0, Z+
  82:	0d 92       	st	X+, r0
  84:	a2 30       	cpi	r26, 0x02	; 2
  86:	b1 07       	cpc	r27, r17
  88:	d9 f7       	brne	.-10     	; 0x80 <__do_copy_data+0xc>

0000008a <__do_clear_bss>:
  8a:	21 e0       	ldi	r18, 0x01	; 1
  8c:	a2 e0       	ldi	r26, 0x02	; 2
  8e:	b1 e0       	ldi	r27, 0x01	; 1
  90:	01 c0       	rjmp	.+2      	; 0x94 <.do_clear_bss_start>

00000092 <.do_clear_bss_loop>:
  92:	1d 92       	st	X+, r1

00000094 <.do_clear_bss_start>:
  94:	ae 32       	cpi	r26, 0x2E	; 46
  96:	b2 07       	cpc	r27, r18
  98:	e1 f7       	brne	.-8      	; 0x92 <.do_clear_bss_loop>
  9a:	0e 94 ae 05 	call	0xb5c	; 0xb5c <main>
  9e:	0c 94 44 06 	jmp	0xc88	; 0xc88 <_exit>

000000a2 <__bad_interrupt>:
  a2:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>

000000a6 <setupWatchdogInterrupt>:


// set Watchdog Timer to periodically generate an interrupt
void setupWatchdogInterrupt( void)
{
	cli();															// ensure the magic below cannot be interrupted
  a6:	f8 94       	cli
	wdt_reset();
  a8:	a8 95       	wdr
	WDTCSR |= (1<<WDCE) | (1<<WDE);									// magic: start the special timed sequence required to change the watchdog control register
  aa:	e0 e6       	ldi	r30, 0x60	; 96
  ac:	f0 e0       	ldi	r31, 0x00	; 0
  ae:	80 81       	ld	r24, Z
  b0:	88 61       	ori	r24, 0x18	; 24
  b2:	80 83       	st	Z, r24
	WDTCSR  =   (1<<WDIE)											// set watchdog:	Watchdog Interrupt Enable
  b4:	86 e4       	ldi	r24, 0x46	; 70
  b6:	80 83       	st	Z, r24
			  | WDT_PRESCALER;										//					Prescaler Value
	sei();
  b8:	78 94       	sei
  ba:	08 95       	ret

000000bc <__vector_6>:
}


ISR( WDT_vect)
{
  bc:	1f 92       	push	r1
  be:	0f 92       	push	r0
  c0:	0f b6       	in	r0, 0x3f	; 63
  c2:	0f 92       	push	r0
  c4:	11 24       	eor	r1, r1
	// note: a watchdog timer reset is automatically done per hardware the ISR is executed, hence wdt_reset() is superfluous here
}
  c6:	0f 90       	pop	r0
  c8:	0f be       	out	0x3f, r0	; 63
  ca:	0f 90       	pop	r0
  cc:	1f 90       	pop	r1
  ce:	18 95       	reti

000000d0 <__vector_10>:
/******************************************************************************
* Interrupt Service Routines
******************************************************************************/

ISR( TIMER1_CAPT_vect )
{
  d0:	1f 92       	push	r1
  d2:	0f 92       	push	r0
  d4:	0f b6       	in	r0, 0x3f	; 63
  d6:	0f 92       	push	r0
  d8:	11 24       	eor	r1, r1
  da:	8f 93       	push	r24
  dc:	9f 93       	push	r25
	TCCR1B ^= (1<<ICES1);					// toggle the Input Capture Edge Selection (because there is no "match any edge" mode)
  de:	80 91 81 00 	lds	r24, 0x0081
  e2:	90 e4       	ldi	r25, 0x40	; 64
  e4:	89 27       	eor	r24, r25
  e6:	80 93 81 00 	sts	0x0081, r24

	if ( signalEdgeNeedsProcessing )		// damn, we are too late: the last edge has not been processed yet in the data-acquisition-loop
  ea:	80 91 0a 01 	lds	r24, 0x010A
  ee:	88 23       	and	r24, r24
  f0:	21 f0       	breq	.+8      	; 0xfa <__vector_10+0x2a>
		signalEdgeMissed = true;
  f2:	81 e0       	ldi	r24, 0x01	; 1
  f4:	80 93 03 01 	sts	0x0103, r24
  f8:	03 c0       	rjmp	.+6      	; 0x100 <__vector_10+0x30>
	else
		signalEdgeNeedsProcessing = true;	// flag the detection of the edge to the processing loop
  fa:	81 e0       	ldi	r24, 0x01	; 1
  fc:	80 93 0a 01 	sts	0x010A, r24
}
 100:	9f 91       	pop	r25
 102:	8f 91       	pop	r24
 104:	0f 90       	pop	r0
 106:	0f be       	out	0x3f, r0	; 63
 108:	0f 90       	pop	r0
 10a:	1f 90       	pop	r1
 10c:	18 95       	reti

0000010e <__vector_13>:


// only reached in case of an error in the data reading/data processing (e.g. when the sensor fails or is not present at all)
ISR( TIMER1_OVF_vect )
{
 10e:	1f 92       	push	r1
 110:	0f 92       	push	r0
 112:	0f b6       	in	r0, 0x3f	; 63
 114:	0f 92       	push	r0
 116:	11 24       	eor	r1, r1
 118:	8f 93       	push	r24
	signalEdgeMissed = true;				// just a trick to force the data processing loop to exit
 11a:	81 e0       	ldi	r24, 0x01	; 1
 11c:	80 93 03 01 	sts	0x0103, r24
}
 120:	8f 91       	pop	r24
 122:	0f 90       	pop	r0
 124:	0f be       	out	0x3f, r0	; 63
 126:	0f 90       	pop	r0
 128:	1f 90       	pop	r1
 12a:	18 95       	reti

0000012c <startInputCaptureTimer>:
******************************************************************************/

void startInputCaptureTimer()
{
	// mode 0: Clear Timer on Compare (CTC) mode with TOP=0xFFFF
	TCCR1A	= (0<<WGM11) | (0<<WGM10);					// mode 0
 12c:	10 92 80 00 	sts	0x0080, r1
	TCCR1B	= (0<<WGM13) | (0<<WGM12);
 130:	e1 e8       	ldi	r30, 0x81	; 129
 132:	f0 e0       	ldi	r31, 0x00	; 0
 134:	10 82       	st	Z, r1
	TCCR1B |= (1<<ICNC1);								// activate noise control for input capture
 136:	80 81       	ld	r24, Z
 138:	80 68       	ori	r24, 0x80	; 128
 13a:	80 83       	st	Z, r24
	TCCR1B |= (0<<ICES1);								// falling edge mode (note: the first edge to be detected is a falling one, the ISR ought to toggle that bit for each detected edge)
 13c:	80 81       	ld	r24, Z
 13e:	80 83       	st	Z, r24
	// enables the Input Capture Interrupt
	// (as well as the Timer Overflow Interrupt in order be able to detect a missing sensor signal, which otherwise would block execution)
	TCCR1B |= PRESCALER_BITMASK;						// starts the timer/counter running
 140:	80 81       	ld	r24, Z
 142:	82 60       	ori	r24, 0x02	; 2
 144:	80 83       	st	Z, r24
	TIMSK1 |= (1<<ICIE1) | (1<<TOIE1);
 146:	ef e6       	ldi	r30, 0x6F	; 111
 148:	f0 e0       	ldi	r31, 0x00	; 0
 14a:	80 81       	ld	r24, Z
 14c:	81 62       	ori	r24, 0x21	; 33
 14e:	80 83       	st	Z, r24
	cli();	// §§§ muss spätestens vor dem letzten Befehl stehen, dieser ist allerdings beliebig (setting TCCR1B, TIMSK1, TCNT1)
 150:	f8 94       	cli
	TCNT1	= 0;										// reset counter value
 152:	10 92 85 00 	sts	0x0085, r1
 156:	10 92 84 00 	sts	0x0084, r1
	ICR1	= 0;										// reset input capture register (neccessary!)
 15a:	10 92 87 00 	sts	0x0087, r1
 15e:	10 92 86 00 	sts	0x0086, r1
 162:	08 95       	ret

00000164 <stopInputCaptureTimer>:
}


void stopInputCaptureTimer( void)
{
	TIMSK1 = 0;											// disable all Timer1 related interrupts
 164:	10 92 6f 00 	sts	0x006F, r1
	TCCR1B &= ~( (1<<CS12) | (1<<CS11) | (1<<CS10) );	// stop timer/counter
 168:	e1 e8       	ldi	r30, 0x81	; 129
 16a:	f0 e0       	ldi	r31, 0x00	; 0
 16c:	80 81       	ld	r24, Z
 16e:	88 7f       	andi	r24, 0xF8	; 248
 170:	80 83       	st	Z, r24
 172:	08 95       	ret

00000174 <acquire_DHT>:
}


// acquires data transfer from the DHT-sensor
bool acquire_DHT()
{
 174:	cf 92       	push	r12
 176:	df 92       	push	r13
 178:	ef 92       	push	r14
 17a:	ff 92       	push	r15
 17c:	0f 93       	push	r16
 17e:	1f 93       	push	r17
 180:	cf 93       	push	r28
 182:	df 93       	push	r29
 184:	00 d0       	rcall	.+0      	; 0x186 <acquire_DHT+0x12>
 186:	cd b7       	in	r28, 0x3d	; 61
 188:	de b7       	in	r29, 0x3e	; 62
	uint8_t		iEdge = 0;							// counts signal level changes
	uint16_t	last_time = 0;						// time of previous signal edge (in microseconds)
	uint16_t	current_time = 0;					// time of current	signal edge (in microseconds)
	uint16_t	duration = 0;						// time between the last two signal edges
	
	volatile uint16_t	var_divisor = ( F_CPU / PRESCALER_VALUE / 1000 );
 18a:	80 ed       	ldi	r24, 0xD0	; 208
 18c:	97 e0       	ldi	r25, 0x07	; 7
 18e:	9a 83       	std	Y+2, r25	; 0x02
 190:	89 83       	std	Y+1, r24	; 0x01

	// ensure High level for some time
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );
 192:	28 9a       	sbi	0x05, 0	; 5
	SENSOR_DDR	|=	(1<<SENSOR_DD_BIT);
 194:	20 9a       	sbi	0x04, 0	; 4
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 196:	8f e9       	ldi	r24, 0x9F	; 159
 198:	9f e0       	ldi	r25, 0x0F	; 15
 19a:	01 97       	sbiw	r24, 0x01	; 1
 19c:	f1 f7       	brne	.-4      	; 0x19a <acquire_DHT+0x26>
 19e:	00 c0       	rjmp	.+0      	; 0x1a0 <acquire_DHT+0x2c>
 1a0:	00 00       	nop
	_delay_ms( 1);									// § how long do we have to wait at least?

	// send start condition (18ms low)
	SENSOR_PORT &= ~(1<<SENSOR_PIN	 );
 1a2:	28 98       	cbi	0x05, 0	; 5
 1a4:	9f ef       	ldi	r25, 0xFF	; 255
 1a6:	20 ee       	ldi	r18, 0xE0	; 224
 1a8:	80 e0       	ldi	r24, 0x00	; 0
 1aa:	91 50       	subi	r25, 0x01	; 1
 1ac:	20 40       	sbci	r18, 0x00	; 0
 1ae:	80 40       	sbci	r24, 0x00	; 0
 1b0:	e1 f7       	brne	.-8      	; 0x1aa <acquire_DHT+0x36>
 1b2:	00 c0       	rjmp	.+0      	; 0x1b4 <acquire_DHT+0x40>
 1b4:	00 00       	nop
	_delay_ms( 18);									// note: in case of the DHT22, 800us would be enough (which can be used to distinguish both models)

	// prepare and start listening
	data0=0; data1=0; data2=0; data3=0; data4=0;
 1b6:	10 92 07 01 	sts	0x0107, r1
 1ba:	10 92 04 01 	sts	0x0104, r1
 1be:	10 92 05 01 	sts	0x0105, r1
 1c2:	10 92 09 01 	sts	0x0109, r1
 1c6:	10 92 06 01 	sts	0x0106, r1
	dataIsValid = false;
 1ca:	10 92 08 01 	sts	0x0108, r1
	iEdge = 0;
	signalEdgeNeedsProcessing = false;
 1ce:	10 92 0a 01 	sts	0x010A, r1
	signalEdgeMissed = false;
 1d2:	10 92 03 01 	sts	0x0103, r1
	cli();											// §§ why exactely is this needed?
 1d6:	f8 94       	cli
	startInputCaptureTimer();
 1d8:	0e 94 96 00 	call	0x12c	; 0x12c <startInputCaptureTimer>
	sei();
 1dc:	78 94       	sei

	// (actively driven = fast) raising edge, then set IO as input with pull-up activ
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );
 1de:	28 9a       	sbi	0x05, 0	; 5
	SENSOR_DDR	&= ~(1<<SENSOR_DD_BIT);
 1e0:	20 98       	cbi	0x04, 0	; 4

// acquires data transfer from the DHT-sensor
bool acquire_DHT()
{
	uint8_t		iEdge = 0;							// counts signal level changes
	uint16_t	last_time = 0;						// time of previous signal edge (in microseconds)
 1e2:	e1 2c       	mov	r14, r1
 1e4:	f1 2c       	mov	r15, r1
	_delay_ms( 18);									// note: in case of the DHT22, 800us would be enough (which can be used to distinguish both models)

	// prepare and start listening
	data0=0; data1=0; data2=0; data3=0; data4=0;
	dataIsValid = false;
	iEdge = 0;
 1e6:	d1 2c       	mov	r13, r1
						{ stopDataTransfer(); break; }		// error
				}
				else										// odd number -> falling edge after 26-28us (representing logic 0) or 70us (representing logic 1)
				{
					uint8_t iByte = (iEdge-5) / 2 / 8;		// 5: first data edge, 2: edges per bit, 8: bits per byte
					uint8_t iBit  = 7 - ( (iEdge-5) / 2 % 8 );		// LSB first
 1e8:	67 e0       	ldi	r22, 0x07	; 7
 1ea:	c6 2e       	mov	r12, r22
						switch ( iByte ) { case 0: data0 &= ~(1<<iBit); break; case 1: data1 &= ~(1<<iBit); break; case 2: data2 &= ~(1<<iBit); break; case 3: data3 &= ~(1<<iBit); break; case 4: data4 &= ~(1<<iBit); break; }
					}
					else if (  duration > 75-TOLERANCE && duration < 75+TOLERANCE )
					{
						// data[iByte] |=	(1<<iBit);			// bit = 1
						switch ( iByte ) { case 0: data0 |= (1<<iBit); break; case 1: data1 |= (1<<iBit); break; case 2: data2 |= (1<<iBit); break; case 3: data3 |= (1<<iBit); break; case 4: data4 |= (1<<iBit); break; }
 1ec:	01 e0       	ldi	r16, 0x01	; 1
 1ee:	10 e0       	ldi	r17, 0x00	; 0
	// (actively driven = fast) raising edge, then set IO as input with pull-up activ
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );
	SENSOR_DDR	&= ~(1<<SENSOR_DD_BIT);
	
	// process data provided from IRQ-driven sensor reading
	while ( ! signalEdgeMissed	)					// note: besides this the loop may be left by "break;"
 1f0:	80 91 03 01 	lds	r24, 0x0103
 1f4:	81 11       	cpse	r24, r1
 1f6:	e7 c0       	rjmp	.+462    	; 0x3c6 <acquire_DHT+0x252>
	{
		if ( signalEdgeNeedsProcessing )			// set by ISR each time a signal level change is detected and its time stored in ICR1
 1f8:	80 91 0a 01 	lds	r24, 0x010A
 1fc:	88 23       	and	r24, r24
 1fe:	c1 f3       	breq	.-16     	; 0x1f0 <acquire_DHT+0x7c>
		{
			iEdge++;
 200:	d3 94       	inc	r13
			// §§§ The following assignment induces VERY STRANGE ERRORNEOUS BEHAVIOUR:
			// current_time = 1000L * ICR1 / ( F_CPU / PRESCALER_VALUE / 1000 );	// §§§ error
			// §§	 The only solution I have found is to put the term ( F_CPU / PRESCALER_VALUE / 1000 ) into a constant.
			//	   Not into a variable, this will fail too ;)
			// current_time = 1000L * ICR1 / CONST_DIVISOR;							// okay
			current_time = 1000L * ICR1 / var_divisor;       // §§§ error	<-------------------- BÖSER FEHLER -------------------->
 202:	20 91 86 00 	lds	r18, 0x0086
 206:	30 91 87 00 	lds	r19, 0x0087
 20a:	49 81       	ldd	r20, Y+1	; 0x01
 20c:	5a 81       	ldd	r21, Y+2	; 0x02
 20e:	a8 ee       	ldi	r26, 0xE8	; 232
 210:	b3 e0       	ldi	r27, 0x03	; 3
 212:	0e 94 13 06 	call	0xc26	; 0xc26 <__umulhisi3>
 216:	9a 01       	movw	r18, r20
 218:	40 e0       	ldi	r20, 0x00	; 0
 21a:	50 e0       	ldi	r21, 0x00	; 0
 21c:	0e 94 f4 05 	call	0xbe8	; 0xbe8 <__divmodsi4>
			duration	 = current_time - last_time;
			last_time	 = current_time;
			
			// at this point, the Input Capture may be triggered again without loss of data, so tell this to be okay now
			asm volatile ("" : : : "memory");				// "compiler barrier" which ensures the compiler does not move the code around
			signalEdgeNeedsProcessing = false;
 220:	10 92 0a 01 	sts	0x010A, r1

			if ( iEdge == 1 )								// begin of start response: 80us low, then 80us high
 224:	91 e0       	ldi	r25, 0x01	; 1
 226:	d9 16       	cp	r13, r25
 228:	09 f4       	brne	.+2      	; 0x22c <acquire_DHT+0xb8>
 22a:	cb c0       	rjmp	.+406    	; 0x3c2 <acquire_DHT+0x24e>
			// current_time = 1000L * ICR1 / ( F_CPU / PRESCALER_VALUE / 1000 );	// §§§ error
			// §§	 The only solution I have found is to put the term ( F_CPU / PRESCALER_VALUE / 1000 ) into a constant.
			//	   Not into a variable, this will fail too ;)
			// current_time = 1000L * ICR1 / CONST_DIVISOR;							// okay
			current_time = 1000L * ICR1 / var_divisor;       // §§§ error	<-------------------- BÖSER FEHLER -------------------->
			duration	 = current_time - last_time;
 22c:	b9 01       	movw	r22, r18
 22e:	6e 19       	sub	r22, r14
 230:	7f 09       	sbc	r23, r15
			asm volatile ("" : : : "memory");				// "compiler barrier" which ensures the compiler does not move the code around
			signalEdgeNeedsProcessing = false;

			if ( iEdge == 1 )								// begin of start response: 80us low, then 80us high
			{}												// the current time is recorded as last_time, nothing else is to be done here
			else if ( iEdge <= 3 )							// end of 80us low (iEdge==2) or end of 80us high (iEdge==3)
 232:	83 e0       	ldi	r24, 0x03	; 3
 234:	8d 15       	cp	r24, r13
 236:	38 f0       	brcs	.+14     	; 0x246 <acquire_DHT+0xd2>
			{
				if (  duration < 80-TOLERANCE || duration > 80+TOLERANCE )
 238:	61 54       	subi	r22, 0x41	; 65
 23a:	71 09       	sbc	r23, r1
 23c:	6f 31       	cpi	r22, 0x1F	; 31
 23e:	71 05       	cpc	r23, r1
 240:	08 f4       	brcc	.+2      	; 0x244 <acquire_DHT+0xd0>
 242:	bf c0       	rjmp	.+382    	; 0x3c2 <acquire_DHT+0x24e>
 244:	bb c0       	rjmp	.+374    	; 0x3bc <acquire_DHT+0x248>
					{ stopDataTransfer(); break; }			// error
			}
			else											// sensor transmits 40 data bits (LSB first)
			{
				if ( ! ( iEdge % 2 ) )						// even number -> rising edge after 50us
 246:	d0 fc       	sbrc	r13, 0
 248:	03 c0       	rjmp	.+6      	; 0x250 <acquire_DHT+0xdc>
				{
					if (  duration < 55-TOLERANCE || duration > 55+TOLERANCE )
 24a:	68 52       	subi	r22, 0x28	; 40
 24c:	71 09       	sbc	r23, r1
 24e:	f6 cf       	rjmp	.-20     	; 0x23c <acquire_DHT+0xc8>
						{ stopDataTransfer(); break; }		// error
				}
				else										// odd number -> falling edge after 26-28us (representing logic 0) or 70us (representing logic 1)
				{
					uint8_t iByte = (iEdge-5) / 2 / 8;		// 5: first data edge, 2: edges per bit, 8: bits per byte
 250:	ad 2d       	mov	r26, r13
 252:	b0 e0       	ldi	r27, 0x00	; 0
 254:	fd 01       	movw	r30, r26
 256:	35 97       	sbiw	r30, 0x05	; 5
 258:	cf 01       	movw	r24, r30
 25a:	f7 fd       	sbrc	r31, 7
 25c:	0f 96       	adiw	r24, 0x0f	; 15
 25e:	54 e0       	ldi	r21, 0x04	; 4
 260:	95 95       	asr	r25
 262:	87 95       	ror	r24
 264:	5a 95       	dec	r21
 266:	e1 f7       	brne	.-8      	; 0x260 <acquire_DHT+0xec>
					uint8_t iBit  = 7 - ( (iEdge-5) / 2 % 8 );		// LSB first
 268:	f7 fd       	sbrc	r31, 7
 26a:	31 96       	adiw	r30, 0x01	; 1
 26c:	f5 95       	asr	r31
 26e:	e7 95       	ror	r30
 270:	e7 70       	andi	r30, 0x07	; 7
 272:	ff 27       	eor	r31, r31
 274:	ac 2d       	mov	r26, r12
 276:	ae 1b       	sub	r26, r30
					if (  duration > 26-TOLERANCE/2 && duration < 28+TOLERANCE/2 )
 278:	fb 01       	movw	r30, r22
 27a:	74 97       	sbiw	r30, 0x14	; 20
 27c:	3f 97       	sbiw	r30, 0x0f	; 15
 27e:	08 f0       	brcs	.+2      	; 0x282 <acquire_DHT+0x10e>
 280:	46 c0       	rjmp	.+140    	; 0x30e <acquire_DHT+0x19a>
					{
						// data[iByte] &= ~(1<<iBit);			// bit = 0
						switch ( iByte ) { case 0: data0 &= ~(1<<iBit); break; case 1: data1 &= ~(1<<iBit); break; case 2: data2 &= ~(1<<iBit); break; case 3: data3 &= ~(1<<iBit); break; case 4: data4 &= ~(1<<iBit); break; }
 282:	82 30       	cpi	r24, 0x02	; 2
 284:	91 05       	cpc	r25, r1
 286:	69 f1       	breq	.+90     	; 0x2e2 <acquire_DHT+0x16e>
 288:	84 f4       	brge	.+32     	; 0x2aa <acquire_DHT+0x136>
 28a:	00 97       	sbiw	r24, 0x00	; 0
 28c:	f9 f0       	breq	.+62     	; 0x2cc <acquire_DHT+0x158>
 28e:	81 30       	cpi	r24, 0x01	; 1
 290:	91 05       	cpc	r25, r1
 292:	09 f0       	breq	.+2      	; 0x296 <acquire_DHT+0x122>
 294:	8d c0       	rjmp	.+282    	; 0x3b0 <acquire_DHT+0x23c>
 296:	0a 2e       	mov	r0, r26
 298:	01 c0       	rjmp	.+2      	; 0x29c <acquire_DHT+0x128>
 29a:	88 0f       	add	r24, r24
 29c:	0a 94       	dec	r0
 29e:	ea f7       	brpl	.-6      	; 0x29a <acquire_DHT+0x126>
 2a0:	80 95       	com	r24
 2a2:	90 91 04 01 	lds	r25, 0x0104
 2a6:	98 23       	and	r25, r24
 2a8:	66 c0       	rjmp	.+204    	; 0x376 <acquire_DHT+0x202>
 2aa:	83 30       	cpi	r24, 0x03	; 3
 2ac:	91 05       	cpc	r25, r1
 2ae:	21 f1       	breq	.+72     	; 0x2f8 <acquire_DHT+0x184>
 2b0:	04 97       	sbiw	r24, 0x04	; 4
 2b2:	09 f0       	breq	.+2      	; 0x2b6 <acquire_DHT+0x142>
 2b4:	7d c0       	rjmp	.+250    	; 0x3b0 <acquire_DHT+0x23c>
 2b6:	c8 01       	movw	r24, r16
 2b8:	0a 2e       	mov	r0, r26
 2ba:	01 c0       	rjmp	.+2      	; 0x2be <acquire_DHT+0x14a>
 2bc:	88 0f       	add	r24, r24
 2be:	0a 94       	dec	r0
 2c0:	ea f7       	brpl	.-6      	; 0x2bc <acquire_DHT+0x148>
 2c2:	80 95       	com	r24
 2c4:	90 91 06 01 	lds	r25, 0x0106
 2c8:	98 23       	and	r25, r24
 2ca:	70 c0       	rjmp	.+224    	; 0x3ac <acquire_DHT+0x238>
 2cc:	c8 01       	movw	r24, r16
 2ce:	0a 2e       	mov	r0, r26
 2d0:	01 c0       	rjmp	.+2      	; 0x2d4 <acquire_DHT+0x160>
 2d2:	88 0f       	add	r24, r24
 2d4:	0a 94       	dec	r0
 2d6:	ea f7       	brpl	.-6      	; 0x2d2 <acquire_DHT+0x15e>
 2d8:	80 95       	com	r24
 2da:	90 91 07 01 	lds	r25, 0x0107
 2de:	98 23       	and	r25, r24
 2e0:	47 c0       	rjmp	.+142    	; 0x370 <acquire_DHT+0x1fc>
 2e2:	c8 01       	movw	r24, r16
 2e4:	0a 2e       	mov	r0, r26
 2e6:	01 c0       	rjmp	.+2      	; 0x2ea <acquire_DHT+0x176>
 2e8:	88 0f       	add	r24, r24
 2ea:	0a 94       	dec	r0
 2ec:	ea f7       	brpl	.-6      	; 0x2e8 <acquire_DHT+0x174>
 2ee:	80 95       	com	r24
 2f0:	90 91 05 01 	lds	r25, 0x0105
 2f4:	98 23       	and	r25, r24
 2f6:	4b c0       	rjmp	.+150    	; 0x38e <acquire_DHT+0x21a>
 2f8:	c8 01       	movw	r24, r16
 2fa:	0a 2e       	mov	r0, r26
 2fc:	01 c0       	rjmp	.+2      	; 0x300 <acquire_DHT+0x18c>
 2fe:	88 0f       	add	r24, r24
 300:	0a 94       	dec	r0
 302:	ea f7       	brpl	.-6      	; 0x2fe <acquire_DHT+0x18a>
 304:	80 95       	com	r24
 306:	90 91 09 01 	lds	r25, 0x0109
 30a:	98 23       	and	r25, r24
 30c:	4c c0       	rjmp	.+152    	; 0x3a6 <acquire_DHT+0x232>
					}
					else if (  duration > 75-TOLERANCE && duration < 75+TOLERANCE )
 30e:	6d 53       	subi	r22, 0x3D	; 61
 310:	71 09       	sbc	r23, r1
 312:	6d 31       	cpi	r22, 0x1D	; 29
 314:	71 05       	cpc	r23, r1
 316:	08 f0       	brcs	.+2      	; 0x31a <acquire_DHT+0x1a6>
 318:	51 c0       	rjmp	.+162    	; 0x3bc <acquire_DHT+0x248>
					{
						// data[iByte] |=	(1<<iBit);			// bit = 1
						switch ( iByte ) { case 0: data0 |= (1<<iBit); break; case 1: data1 |= (1<<iBit); break; case 2: data2 |= (1<<iBit); break; case 3: data3 |= (1<<iBit); break; case 4: data4 |= (1<<iBit); break; }
 31a:	82 30       	cpi	r24, 0x02	; 2
 31c:	91 05       	cpc	r25, r1
 31e:	71 f1       	breq	.+92     	; 0x37c <acquire_DHT+0x208>
 320:	7c f4       	brge	.+30     	; 0x340 <acquire_DHT+0x1cc>
 322:	00 97       	sbiw	r24, 0x00	; 0
 324:	e1 f0       	breq	.+56     	; 0x35e <acquire_DHT+0x1ea>
 326:	81 30       	cpi	r24, 0x01	; 1
 328:	91 05       	cpc	r25, r1
 32a:	09 f0       	breq	.+2      	; 0x32e <acquire_DHT+0x1ba>
 32c:	41 c0       	rjmp	.+130    	; 0x3b0 <acquire_DHT+0x23c>
 32e:	0a 2e       	mov	r0, r26
 330:	01 c0       	rjmp	.+2      	; 0x334 <acquire_DHT+0x1c0>
 332:	88 0f       	add	r24, r24
 334:	0a 94       	dec	r0
 336:	ea f7       	brpl	.-6      	; 0x332 <acquire_DHT+0x1be>
 338:	90 91 04 01 	lds	r25, 0x0104
 33c:	98 2b       	or	r25, r24
 33e:	1b c0       	rjmp	.+54     	; 0x376 <acquire_DHT+0x202>
 340:	83 30       	cpi	r24, 0x03	; 3
 342:	91 05       	cpc	r25, r1
 344:	39 f1       	breq	.+78     	; 0x394 <acquire_DHT+0x220>
 346:	04 97       	sbiw	r24, 0x04	; 4
 348:	99 f5       	brne	.+102    	; 0x3b0 <acquire_DHT+0x23c>
 34a:	c8 01       	movw	r24, r16
 34c:	0a 2e       	mov	r0, r26
 34e:	01 c0       	rjmp	.+2      	; 0x352 <acquire_DHT+0x1de>
 350:	88 0f       	add	r24, r24
 352:	0a 94       	dec	r0
 354:	ea f7       	brpl	.-6      	; 0x350 <acquire_DHT+0x1dc>
 356:	90 91 06 01 	lds	r25, 0x0106
 35a:	98 2b       	or	r25, r24
 35c:	27 c0       	rjmp	.+78     	; 0x3ac <acquire_DHT+0x238>
 35e:	c8 01       	movw	r24, r16
 360:	0a 2e       	mov	r0, r26
 362:	01 c0       	rjmp	.+2      	; 0x366 <acquire_DHT+0x1f2>
 364:	88 0f       	add	r24, r24
 366:	0a 94       	dec	r0
 368:	ea f7       	brpl	.-6      	; 0x364 <acquire_DHT+0x1f0>
 36a:	90 91 07 01 	lds	r25, 0x0107
 36e:	98 2b       	or	r25, r24
 370:	90 93 07 01 	sts	0x0107, r25
 374:	1d c0       	rjmp	.+58     	; 0x3b0 <acquire_DHT+0x23c>
 376:	90 93 04 01 	sts	0x0104, r25
 37a:	1a c0       	rjmp	.+52     	; 0x3b0 <acquire_DHT+0x23c>
 37c:	c8 01       	movw	r24, r16
 37e:	0a 2e       	mov	r0, r26
 380:	01 c0       	rjmp	.+2      	; 0x384 <acquire_DHT+0x210>
 382:	88 0f       	add	r24, r24
 384:	0a 94       	dec	r0
 386:	ea f7       	brpl	.-6      	; 0x382 <acquire_DHT+0x20e>
 388:	90 91 05 01 	lds	r25, 0x0105
 38c:	98 2b       	or	r25, r24
 38e:	90 93 05 01 	sts	0x0105, r25
 392:	0e c0       	rjmp	.+28     	; 0x3b0 <acquire_DHT+0x23c>
 394:	c8 01       	movw	r24, r16
 396:	0a 2e       	mov	r0, r26
 398:	01 c0       	rjmp	.+2      	; 0x39c <acquire_DHT+0x228>
 39a:	88 0f       	add	r24, r24
 39c:	0a 94       	dec	r0
 39e:	ea f7       	brpl	.-6      	; 0x39a <acquire_DHT+0x226>
 3a0:	90 91 09 01 	lds	r25, 0x0109
 3a4:	98 2b       	or	r25, r24
 3a6:	90 93 09 01 	sts	0x0109, r25
 3aa:	02 c0       	rjmp	.+4      	; 0x3b0 <acquire_DHT+0x23c>
 3ac:	90 93 06 01 	sts	0x0106, r25
					}
					else
						{ stopDataTransfer(); break; }		// error
					if ( iEdge == 83 )						// final bit edge
 3b0:	93 e5       	ldi	r25, 0x53	; 83
 3b2:	d9 12       	cpse	r13, r25
 3b4:	06 c0       	rjmp	.+12     	; 0x3c2 <acquire_DHT+0x24e>
					{
						dataIsValid = true;					// SUCCESS
 3b6:	81 e0       	ldi	r24, 0x01	; 1
 3b8:	80 93 08 01 	sts	0x0108, r24
						stopDataTransfer(); break;
 3bc:	0e 94 b2 00 	call	0x164	; 0x164 <stopInputCaptureTimer>
 3c0:	02 c0       	rjmp	.+4      	; 0x3c6 <acquire_DHT+0x252>
}


// acquires data transfer from the DHT-sensor
bool acquire_DHT()
{
 3c2:	79 01       	movw	r14, r18
 3c4:	15 cf       	rjmp	.-470    	; 0x1f0 <acquire_DHT+0x7c>
			}	// if ( iEdge <= 3 ) ... else
		}	// if ( signalEdgeNeedsProcessing )
	}	// while ( ! signalEdgeMissed ) - or left by "break;"

	// stop timer/counter1 and reset port pin
	stopInputCaptureTimer();
 3c6:	0e 94 b2 00 	call	0x164	; 0x164 <stopInputCaptureTimer>
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );				// high
 3ca:	28 9a       	sbi	0x05, 0	; 5
	SENSOR_DDR	|=	(1<<SENSOR_DD_BIT);				// out
 3cc:	20 9a       	sbi	0x04, 0	; 4

	// check checksum
	uint8_t sum = (uint8_t)(data0 + data1 + data2 + data3);
 3ce:	80 91 04 01 	lds	r24, 0x0104
 3d2:	90 91 07 01 	lds	r25, 0x0107
 3d6:	89 0f       	add	r24, r25
 3d8:	90 91 05 01 	lds	r25, 0x0105
 3dc:	89 0f       	add	r24, r25
 3de:	90 91 09 01 	lds	r25, 0x0109
 3e2:	89 0f       	add	r24, r25
	if ( sum != data4 )
 3e4:	90 91 06 01 	lds	r25, 0x0106
 3e8:	89 13       	cpse	r24, r25
		dataIsValid = false;
 3ea:	10 92 08 01 	sts	0x0108, r1

	return	dataIsValid;
}	// bool acquire_DHT()
 3ee:	80 91 08 01 	lds	r24, 0x0108
 3f2:	0f 90       	pop	r0
 3f4:	0f 90       	pop	r0
 3f6:	df 91       	pop	r29
 3f8:	cf 91       	pop	r28
 3fa:	1f 91       	pop	r17
 3fc:	0f 91       	pop	r16
 3fe:	ff 90       	pop	r15
 400:	ef 90       	pop	r14
 402:	df 90       	pop	r13
 404:	cf 90       	pop	r12
 406:	08 95       	ret

00000408 <get_humidity>:

#if DHT_TYPE == DHT_TYPE_DHT11

	uint8_t get_humidity( void)
	{
		if ( dataIsValid )
 408:	80 91 08 01 	lds	r24, 0x0108
 40c:	88 23       	and	r24, r24
 40e:	19 f0       	breq	.+6      	; 0x416 <get_humidity+0xe>
			return data0;
 410:	80 91 07 01 	lds	r24, 0x0107
 414:	08 95       	ret
		else
			return 0;
 416:	80 e0       	ldi	r24, 0x00	; 0
	}
 418:	08 95       	ret

0000041a <get_temperature>:

	int8_t get_temperature( void)
	{
		if ( dataIsValid )
 41a:	80 91 08 01 	lds	r24, 0x0108
 41e:	88 23       	and	r24, r24
 420:	19 f0       	breq	.+6      	; 0x428 <get_temperature+0xe>
			return data2;
 422:	80 91 05 01 	lds	r24, 0x0105
 426:	08 95       	ret
		else
			return 0;	// § may be better to use an impossible value too
 428:	80 e0       	ldi	r24, 0x00	; 0
	}
 42a:	08 95       	ret

0000042c <spi_init>:

// Initialize pins and registers for spi communication
void spi_init()
{
	// define port pins as input
    DDR_SPI &= ~( (1<<DD_MISO) );
 42c:	24 98       	cbi	0x04, 4	; 4
	// define port pins as output
    DDR_SPI |=  ( (1<<DD_MOSI) | (1<<DD_SS) | (1<<DD_SCK) );
 42e:	84 b1       	in	r24, 0x04	; 4
 430:	8c 62       	ori	r24, 0x2C	; 44
 432:	84 b9       	out	0x04, r24	; 4
    
    SPCR = (   (1<<SPE)				// SPI Enable
 434:	81 e5       	ldi	r24, 0x51	; 81
 436:	8c bd       	out	0x2c, r24	; 44
             | (0<<SPR1)
			 | (1<<SPR0)			// SPI Clock Rate
             | (0<<CPOL)			// Clock Polarity (0:SCK low / 1:SCK hi when idle)		§ may need to be adapted
             | (0<<CPHA)			// Clock Phase (0:leading / 1:trailing edge sampling)	§ may need to be adapted
		   );
    SPSR = (1<<SPI2X);				// Double Clock Rate = 8 MHz (§ use with care, since not all SPI devices support this)
 438:	81 e0       	ldi	r24, 0x01	; 1
 43a:	8d bd       	out	0x2d, r24	; 45
 43c:	08 95       	ret

0000043e <spi_stop>:


// Deactivates the SPI module (use in order to save current when going to sleep/power down)
void spi_stop()
{
    SPCR &= ~(1<<SPE);				// SPI Enable
 43e:	8c b5       	in	r24, 0x2c	; 44
 440:	8f 7b       	andi	r24, 0xBF	; 191
 442:	8c bd       	out	0x2c, r24	; 44
 444:	08 95       	ret

00000446 <spi_transfer_byte>:


// Writes one byte to target device and returns the received one
uint8_t spi_transfer_byte( uint8_t data)
{
    SPDR = data;
 446:	8e bd       	out	0x2e, r24	; 46
    while ( !( SPSR & (1<<SPIF) ) );
 448:	0d b4       	in	r0, 0x2d	; 45
 44a:	07 fe       	sbrs	r0, 7
 44c:	fd cf       	rjmp	.-6      	; 0x448 <spi_transfer_byte+0x2>
    return SPDR;
 44e:	8e b5       	in	r24, 0x2e	; 46
}
 450:	08 95       	ret

00000452 <spi_transfer>:


// Writes an byte-array of len bytes to target device and returns the bytes received
void spi_transfer( uint8_t * dataout, uint8_t * datain, uint8_t len)
{
 452:	26 2f       	mov	r18, r22
	for ( uint8_t i = 0; i < len; i++ )
 454:	fb 01       	movw	r30, r22
 456:	3e 2f       	mov	r19, r30
 458:	32 1b       	sub	r19, r18
 45a:	34 17       	cp	r19, r20
 45c:	50 f4       	brcc	.+20     	; 0x472 <spi_transfer+0x20>
	{
		SPDR = dataout[i];
 45e:	dc 01       	movw	r26, r24
 460:	3d 91       	ld	r19, X+
 462:	cd 01       	movw	r24, r26
 464:	3e bd       	out	0x2e, r19	; 46
		while ( !( SPSR & (1<<SPIF) ) );
 466:	0d b4       	in	r0, 0x2d	; 45
 468:	07 fe       	sbrs	r0, 7
 46a:	fd cf       	rjmp	.-6      	; 0x466 <spi_transfer+0x14>
		datain[i] = SPDR;
 46c:	3e b5       	in	r19, 0x2e	; 46
 46e:	31 93       	st	Z+, r19
 470:	f2 cf       	rjmp	.-28     	; 0x456 <spi_transfer+0x4>
	}
}
 472:	08 95       	ret

00000474 <spi_transmit>:


// Writes an byte-array of len bytes to target device and discards the bytes received
void spi_transmit( uint8_t * dataout, uint8_t len)
{
 474:	28 2f       	mov	r18, r24
	for ( uint8_t i = 0; i < len; i++)
 476:	fc 01       	movw	r30, r24
 478:	8e 2f       	mov	r24, r30
 47a:	82 1b       	sub	r24, r18
 47c:	86 17       	cp	r24, r22
 47e:	30 f4       	brcc	.+12     	; 0x48c <spi_transmit+0x18>
	{
		SPDR = dataout[i];
 480:	81 91       	ld	r24, Z+
 482:	8e bd       	out	0x2e, r24	; 46
		while ( !( SPSR & (1<<SPIF) ) );
 484:	0d b4       	in	r0, 0x2d	; 45
 486:	07 fe       	sbrs	r0, 7
 488:	fd cf       	rjmp	.-6      	; 0x484 <spi_transmit+0x10>
 48a:	f6 cf       	rjmp	.-20     	; 0x478 <spi_transmit+0x4>
	}
}
 48c:	08 95       	ret

0000048e <__vector_2>:
#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega88A__) || defined(__AVR_ATmega168__)
ISR( INT1_vect )
#else
#	error MCU MODEL NOT SUPPORTED
#endif // defined(__AVR_ATmega8__) || defined(__AVR_ATmega88A__) || defined(__AVR_ATmega168__)
{
 48e:	1f 92       	push	r1
 490:	0f 92       	push	r0
 492:	0f b6       	in	r0, 0x3f	; 63
 494:	0f 92       	push	r0
 496:	11 24       	eor	r1, r1
 498:	8f 93       	push	r24
	// just flag the IRQ (processing of status/data as well as resetting of the flag variable has to be done in the main loop)
	lib_nRF24L01_IRQ_scheduled = true;
 49a:	81 e0       	ldi	r24, 0x01	; 1
 49c:	80 93 2d 01 	sts	0x012D, r24
}
 4a0:	8f 91       	pop	r24
 4a2:	0f 90       	pop	r0
 4a4:	0f be       	out	0x3f, r0	; 63
 4a6:	0f 90       	pop	r0
 4a8:	1f 90       	pop	r1
 4aa:	18 95       	reti

000004ac <lib_nRF24L01_reuse_TX_FIFO>:


// schedules the current TX FIFO to be sent again (after a packet is lost)
void lib_nRF24L01_reuse_TX_FIFO( void)
{
	lib_nRF24L01_EXECUTE(
 4ac:	5d 98       	cbi	0x0b, 5	; 11
 4ae:	83 ee       	ldi	r24, 0xE3	; 227
 4b0:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 4b4:	5d 9a       	sbi	0x0b, 5	; 11
 4b6:	08 95       	ret

000004b8 <lib_nRF24L01_flush_TX_FIFO>:
}


void lib_nRF24L01_flush_TX_FIFO( void)
{
	lib_nRF24L01_EXECUTE(
 4b8:	5d 98       	cbi	0x0b, 5	; 11
 4ba:	81 ee       	ldi	r24, 0xE1	; 225
 4bc:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 4c0:	5d 9a       	sbi	0x0b, 5	; 11
 4c2:	08 95       	ret

000004c4 <lib_nRF24L01_flush_RX_FIFO>:
}


void lib_nRF24L01_flush_RX_FIFO( void)
{
	lib_nRF24L01_EXECUTE(
 4c4:	5d 98       	cbi	0x0b, 5	; 11
 4c6:	81 ee       	ldi	r24, 0xE1	; 225
 4c8:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 4cc:	5d 9a       	sbi	0x0b, 5	; 11
 4ce:	08 95       	ret

000004d0 <lib_nRF24L01_set_CE_high>:
//-----------------------------------------------------------------------------

// Chip Enable Control: start RX/TX operation
void lib_nRF24L01_set_CE_high()
{
	lib_nRF24L01_CONTROL_PORT |=  _BV(lib_nRF24L01_CE_PIN );
 4d0:	5c 9a       	sbi	0x0b, 4	; 11
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 4d2:	85 e1       	ldi	r24, 0x15	; 21
 4d4:	8a 95       	dec	r24
 4d6:	f1 f7       	brne	.-4      	; 0x4d4 <lib_nRF24L01_set_CE_high+0x4>
 4d8:	00 00       	nop
	_delay_us( nRF24L01_DELAY_CE_HIGH_2_CSN_LOW);
	currentState |=  STATE_BITMASK_ACTIVE;
 4da:	80 91 02 01 	lds	r24, 0x0102
 4de:	88 60       	ori	r24, 0x08	; 8
 4e0:	80 93 02 01 	sts	0x0102, r24
 4e4:	08 95       	ret

000004e6 <lib_nRF24L01_set_CE_low>:


// Chip Enable Control: stop RX/TX operation
void lib_nRF24L01_set_CE_low()
{
	lib_nRF24L01_CONTROL_PORT &= ~_BV(lib_nRF24L01_CE_PIN );
 4e6:	5c 98       	cbi	0x0b, 4	; 11
	currentState &= ~STATE_BITMASK_ACTIVE;
 4e8:	80 91 02 01 	lds	r24, 0x0102
 4ec:	87 7f       	andi	r24, 0xF7	; 247
 4ee:	80 93 02 01 	sts	0x0102, r24
 4f2:	08 95       	ret

000004f4 <lib_nRF24L01_init_MCU>:

// Initializes MCU-pins to communicate with the lib_nRF24L01.
void lib_nRF24L01_init_MCU()
{
	// Initialize SPI in mode 0 (CPOL=0 und CPHA=0)
	spi_init();						// §§ uses the libs default SPI mode without checking whether this is appropriate
 4f4:	0e 94 16 02 	call	0x42c	; 0x42c <spi_init>

	// Define CSN- and CE-pins as output and set them to default values
	lib_nRF24L01_CONTROL_DDR |= _BV(lib_nRF24L01_CSN_PIN) | _BV(lib_nRF24L01_CE_PIN);	// § note: this coding abuses the identity of port value register bit position as well as data direction register bit position
 4f8:	8a b1       	in	r24, 0x0a	; 10
 4fa:	80 63       	ori	r24, 0x30	; 48
 4fc:	8a b9       	out	0x0a, r24	; 10
	lib_nRF24L01_SET_CSN_HIGH;		// SPI Chip Select = false
 4fe:	5d 9a       	sbi	0x0b, 5	; 11
	lib_nRF24L01_set_CE_low();		// nRF24L01 Chip Enable = false (i.e. the nRF24L01 stays in passive mode)
 500:	0e 94 73 02 	call	0x4e6	; 0x4e6 <lib_nRF24L01_set_CE_low>
	MCUCR |=  _BV(ISC11);			// Interrupt Sense Control Bits: generate external interrupt INT0 on falling edge
	MCUCR &= ~_BV(ISC10);
	GICR  |=  _BV(INT1);			// Activate INT0
#elif defined(__AVR_ATmega88A__) || defined(__AVR_ATmega168__) || defined(__AVR_ATmega328__)
	// ... external interrupt 1 (PD3)
	EICRA |=  _BV(ISC11);			// External Interrupt Control Bits: generate interrupt on falling edge for INT0
 504:	e9 e6       	ldi	r30, 0x69	; 105
 506:	f0 e0       	ldi	r31, 0x00	; 0
 508:	80 81       	ld	r24, Z
 50a:	88 60       	ori	r24, 0x08	; 8
 50c:	80 83       	st	Z, r24
	EICRA &= ~_BV(ISC10);
 50e:	80 81       	ld	r24, Z
 510:	8b 7f       	andi	r24, 0xFB	; 251
 512:	80 83       	st	Z, r24
	EIMSK |=  _BV(INT1);			// Activate INT0
 514:	e9 9a       	sbi	0x1d, 1	; 29
 516:	08 95       	ret

00000518 <lib_nRF24L01_TriggerSingleTrans>:

// Start single transmission by a high pulse on CE pin. Note: 10uS is the minimal allowable pulse length.
// If the CE signal is already high, this function returns without doing anything.
void lib_nRF24L01_TriggerSingleTrans()
{
	if ( ! (currentState & STATE_BITMASK_ACTIVE) )
 518:	80 91 02 01 	lds	r24, 0x0102
 51c:	83 fd       	sbrc	r24, 3
 51e:	08 c0       	rjmp	.+16     	; 0x530 <lib_nRF24L01_TriggerSingleTrans+0x18>
	{
		lib_nRF24L01_set_CE_high();
 520:	0e 94 68 02 	call	0x4d0	; 0x4d0 <lib_nRF24L01_set_CE_high>
 524:	8a e6       	ldi	r24, 0x6A	; 106
 526:	8a 95       	dec	r24
 528:	f1 f7       	brne	.-4      	; 0x526 <lib_nRF24L01_TriggerSingleTrans+0xe>
 52a:	00 c0       	rjmp	.+0      	; 0x52c <lib_nRF24L01_TriggerSingleTrans+0x14>
		_delay_us( 2 * nRF24L01_DELAY_MIN_CE_HIGH);		// § Caution: there are versions of nRF24L01 modules, which have been reported not to work with a delay of 10us.
		lib_nRF24L01_set_CE_low();
 52c:	0c 94 73 02 	jmp	0x4e6	; 0x4e6 <lib_nRF24L01_set_CE_low>
 530:	08 95       	ret

00000532 <lib_nRF24L01_start>:

// Puts the nRF24L01 into operation (i.e. receiving or transmitting messages depending on the current configuration).
// If the nRF24L01 is currently active, the operation is stopped and then restarted in order to make sure it operates according to the current mode configuration.
void lib_nRF24L01_start()
{
	if (   (currentState & STATE_BITMASK_ACTIVE) )
 532:	80 91 02 01 	lds	r24, 0x0102
 536:	83 ff       	sbrs	r24, 3
 538:	06 c0       	rjmp	.+12     	; 0x546 <lib_nRF24L01_start+0x14>
	{
		lib_nRF24L01_set_CE_low();						// stop active operation (switch into standby mode)
 53a:	0e 94 73 02 	call	0x4e6	; 0x4e6 <lib_nRF24L01_set_CE_low>
 53e:	85 e3       	ldi	r24, 0x35	; 53
 540:	8a 95       	dec	r24
 542:	f1 f7       	brne	.-4      	; 0x540 <lib_nRF24L01_start+0xe>
 544:	00 00       	nop
		_delay_us( nRF24L01_DELAY_CE_LOW_2_CE_HIGH);
	}
	lib_nRF24L01_set_CE_high();							// start active operation
 546:	0e 94 68 02 	call	0x4d0	; 0x4d0 <lib_nRF24L01_set_CE_high>

	// The nRF24L01+ needs 130us to sync its PLL and start operation after CE goes high.
	// In RX mode we do not have to bother about that, since polling/IRQ-driven message receiving will always work as expected.
	// But in TX mode we may ought to ensure the TX FIFO cannot be written to before the nRF24L01+ is ready. 	§§ check if really neccessary
	if ( ! (currentState & STATE_BITMASK_RX_MODE) )
 54a:	80 91 02 01 	lds	r24, 0x0102
 54e:	82 fd       	sbrc	r24, 2
 550:	06 c0       	rjmp	.+12     	; 0x55e <lib_nRF24L01_start+0x2c>
 552:	87 e0       	ldi	r24, 0x07	; 7
 554:	92 e0       	ldi	r25, 0x02	; 2
 556:	01 97       	sbiw	r24, 0x01	; 1
 558:	f1 f7       	brne	.-4      	; 0x556 <lib_nRF24L01_start+0x24>
 55a:	00 c0       	rjmp	.+0      	; 0x55c <lib_nRF24L01_start+0x2a>
 55c:	00 00       	nop
 55e:	08 95       	ret

00000560 <lib_nRF24L01_stop>:


// Puts the nRF24L01+ into standby-mode (i.e. leaves TX/RX active modes)
void lib_nRF24L01_stop()
{
	lib_nRF24L01_set_CE_low();
 560:	0c 94 73 02 	jmp	0x4e6	; 0x4e6 <lib_nRF24L01_set_CE_low>

00000564 <lib_nRF24L01_get_regbyte>:
// low level functions (read/write nRF24L01+ registers)
//-----------------------------------------------------------------------------

// Reads one byte from the given nRF24L01-module register
uint8_t lib_nRF24L01_get_regbyte( uint8_t reg)
{
 564:	cf 93       	push	r28
 566:	df 93       	push	r29
 568:	1f 92       	push	r1
 56a:	cd b7       	in	r28, 0x3d	; 61
 56c:	de b7       	in	r29, 0x3e	; 62
	uint8_t byteval;
	lib_nRF24L01_EXECUTE(
 56e:	5d 98       	cbi	0x0b, 5	; 11
 570:	8f 71       	andi	r24, 0x1F	; 31
 572:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 576:	41 e0       	ldi	r20, 0x01	; 1
 578:	be 01       	movw	r22, r28
 57a:	6f 5f       	subi	r22, 0xFF	; 255
 57c:	7f 4f       	sbci	r23, 0xFF	; 255
 57e:	cb 01       	movw	r24, r22
 580:	0e 94 29 02 	call	0x452	; 0x452 <spi_transfer>
 584:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_R_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_transfer_sync( &byteval, &byteval, 1);
	)
	return byteval;
}
 586:	89 81       	ldd	r24, Y+1	; 0x01
 588:	0f 90       	pop	r0
 58a:	df 91       	pop	r29
 58c:	cf 91       	pop	r28
 58e:	08 95       	ret

00000590 <lib_nRF24L01_set_regbyte>:


// Writes one byte into the given nRF24L01-module register
void lib_nRF24L01_set_regbyte( uint8_t reg, uint8_t value)
{
 590:	cf 93       	push	r28
 592:	df 93       	push	r29
 594:	1f 92       	push	r1
 596:	cd b7       	in	r28, 0x3d	; 61
 598:	de b7       	in	r29, 0x3e	; 62
	lib_nRF24L01_EXECUTE(
 59a:	5d 98       	cbi	0x0b, 5	; 11
 59c:	8f 71       	andi	r24, 0x1F	; 31
 59e:	80 62       	ori	r24, 0x20	; 32
 5a0:	69 83       	std	Y+1, r22	; 0x01
 5a2:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 5a6:	69 81       	ldd	r22, Y+1	; 0x01
 5a8:	86 2f       	mov	r24, r22
 5aa:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 5ae:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_W_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_fast_shift( value);
	)
}
 5b0:	0f 90       	pop	r0
 5b2:	df 91       	pop	r29
 5b4:	cf 91       	pop	r28
 5b6:	08 95       	ret

000005b8 <lib_nRF24L01_invoke_RX_mode>:

// Sets nRF24L01-registers for RX mode and powers it up into standby mode.
// If the nRF24L01 is currently set active, this state will NOT be left. In this case you need to stop/restart active operation in order to activate the RX mode.
void lib_nRF24L01_invoke_RX_mode()
{
	lib_nRF24L01_set_regbyte( nRF_REG_CONFIG,   lib_nRF24L01_CONFIG
 5b8:	6f e0       	ldi	r22, 0x0F	; 15
 5ba:	80 e0       	ldi	r24, 0x00	; 0
 5bc:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
											  | nRF_REGBITMASK_CONFIG_PWR_UP
											  | nRF_REGBITMASK_CONFIG_PRIM_RX
							);

	if ( ! (currentState & STATE_BITMASK_PWR_UP) )
 5c0:	80 91 02 01 	lds	r24, 0x0102
 5c4:	81 fd       	sbrc	r24, 1
 5c6:	06 c0       	rjmp	.+12     	; 0x5d4 <lib_nRF24L01_invoke_RX_mode+0x1c>
 5c8:	8f e6       	ldi	r24, 0x6F	; 111
 5ca:	97 e1       	ldi	r25, 0x17	; 23
 5cc:	01 97       	sbiw	r24, 0x01	; 1
 5ce:	f1 f7       	brne	.-4      	; 0x5cc <lib_nRF24L01_invoke_RX_mode+0x14>
 5d0:	00 c0       	rjmp	.+0      	; 0x5d2 <lib_nRF24L01_invoke_RX_mode+0x1a>
 5d2:	00 00       	nop
		_delay_us( nRF24L01_DELAY_POWERUP);

	currentState |= ( STATE_BITMASK_PWR_UP | STATE_BITMASK_RX_MODE );
 5d4:	80 91 02 01 	lds	r24, 0x0102
 5d8:	86 60       	ori	r24, 0x06	; 6
 5da:	80 93 02 01 	sts	0x0102, r24
 5de:	08 95       	ret

000005e0 <lib_nRF24L01_invoke_TX_mode>:
// The PTX-device address will be set to the address assigned to this RX data pipe.
// Note: when using "auto acknowledgement", RX_Address_Pipe_0 must be the same as the TX-address, since it is used to receive the ack payload from the receiver.
// If the nRF24L01 is currently set active, this state will NOT be left. In this case you need to stop/restart active operation in order to activate the TX mode.
void lib_nRF24L01_invoke_TX_mode( void)
{
	lib_nRF24L01_set_regbyte( nRF_REG_CONFIG,   lib_nRF24L01_CONFIG
 5e0:	6e e0       	ldi	r22, 0x0E	; 14
 5e2:	80 e0       	ldi	r24, 0x00	; 0
 5e4:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
											  | nRF_REGBITMASK_CONFIG_PWR_UP
							);

	if ( ! (currentState & STATE_BITMASK_PWR_UP) )
 5e8:	80 91 02 01 	lds	r24, 0x0102
 5ec:	81 fd       	sbrc	r24, 1
 5ee:	06 c0       	rjmp	.+12     	; 0x5fc <lib_nRF24L01_invoke_TX_mode+0x1c>
 5f0:	8f e6       	ldi	r24, 0x6F	; 111
 5f2:	97 e1       	ldi	r25, 0x17	; 23
 5f4:	01 97       	sbiw	r24, 0x01	; 1
 5f6:	f1 f7       	brne	.-4      	; 0x5f4 <lib_nRF24L01_invoke_TX_mode+0x14>
 5f8:	00 c0       	rjmp	.+0      	; 0x5fa <lib_nRF24L01_invoke_TX_mode+0x1a>
 5fa:	00 00       	nop
		_delay_us( nRF24L01_DELAY_POWERUP);

	currentState |=  STATE_BITMASK_PWR_UP;
	currentState &= ~STATE_BITMASK_RX_MODE;
 5fc:	80 91 02 01 	lds	r24, 0x0102
 600:	8b 7f       	andi	r24, 0xFB	; 251
 602:	82 60       	ori	r24, 0x02	; 2
 604:	80 93 02 01 	sts	0x0102, r24
 608:	08 95       	ret

0000060a <lib_nRF24L01_get_data>:


// Read at most maxBytes bytes from received packet data into array payload.
// Note that the nRF24L01+ deletes the whole FIFO slot afterwards.
void lib_nRF24L01_get_data( uint8_t * payload, uint8_t maxBytes)
{
 60a:	ff 92       	push	r15
 60c:	0f 93       	push	r16
 60e:	1f 93       	push	r17
 610:	cf 93       	push	r28
 612:	df 93       	push	r29
 614:	1f 92       	push	r1
 616:	cd b7       	in	r28, 0x3d	; 61
 618:	de b7       	in	r29, 0x3e	; 62
 61a:	8c 01       	movw	r16, r24
 61c:	f6 2e       	mov	r15, r22
	uint8_t payloadWidth;

#ifdef DEBUG2
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 100);
#endif
	lib_nRF24L01_EXECUTE(
 61e:	5d 98       	cbi	0x0b, 5	; 11
 620:	80 e6       	ldi	r24, 0x60	; 96
 622:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 626:	61 e0       	ldi	r22, 0x01	; 1
 628:	ce 01       	movw	r24, r28
 62a:	01 96       	adiw	r24, 0x01	; 1
 62c:	0e 94 3a 02 	call	0x474	; 0x474 <spi_transmit>
 630:	5d 9a       	sbi	0x0b, 5	; 11
		spi_transmit_sync( &payloadWidth, 1);											// Get payload width	§§ korrekt?
	)
#ifdef DEBUG2
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 100);
#endif
	lib_nRF24L01_EXECUTE(
 632:	5d 98       	cbi	0x0b, 5	; 11
 634:	81 e6       	ldi	r24, 0x61	; 97
 636:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 63a:	89 81       	ldd	r24, Y+1	; 0x01
 63c:	4f 2d       	mov	r20, r15
 63e:	f8 16       	cp	r15, r24
 640:	08 f4       	brcc	.+2      	; 0x644 <lib_nRF24L01_get_data+0x3a>
 642:	48 2f       	mov	r20, r24
 644:	b8 01       	movw	r22, r16
 646:	c8 01       	movw	r24, r16
 648:	0e 94 29 02 	call	0x452	; 0x452 <spi_transfer>
 64c:	5d 9a       	sbi	0x0b, 5	; 11
		spi_transfer_sync( payload, payload, max( payloadWidth, maxBytes) );			// Read payload
	)
#ifdef DEBUG2
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 100);
#endif
	lib_nRF24L01_set_regbyte( nRF_REG_STATUS, nRF_REGBITMASK_STATUS_RX_DR);				// Reset RX_DR flag
 64e:	60 e4       	ldi	r22, 0x40	; 64
 650:	87 e0       	ldi	r24, 0x07	; 7
 652:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
}
 656:	0f 90       	pop	r0
 658:	df 91       	pop	r29
 65a:	cf 91       	pop	r28
 65c:	1f 91       	pop	r17
 65e:	0f 91       	pop	r16
 660:	ff 90       	pop	r15
 662:	08 95       	ret

00000664 <lib_nRF24L01_read_register>:


// Reads an array of bytes from the given start position in the nRF24L01-module registers.
// Returns value of nRF24L01 status register before any changes are done.
void lib_nRF24L01_read_register( uint8_t reg, uint8_t * value, uint8_t len)
{
 664:	0f 93       	push	r16
 666:	1f 93       	push	r17
 668:	cf 93       	push	r28
 66a:	df 93       	push	r29
 66c:	1f 92       	push	r1
 66e:	cd b7       	in	r28, 0x3d	; 61
 670:	de b7       	in	r29, 0x3e	; 62
 672:	8b 01       	movw	r16, r22
	lib_nRF24L01_EXECUTE(
 674:	5d 98       	cbi	0x0b, 5	; 11
 676:	8f 71       	andi	r24, 0x1F	; 31
 678:	49 83       	std	Y+1, r20	; 0x01
 67a:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 67e:	49 81       	ldd	r20, Y+1	; 0x01
 680:	b8 01       	movw	r22, r16
 682:	c8 01       	movw	r24, r16
 684:	0e 94 29 02 	call	0x452	; 0x452 <spi_transfer>
 688:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_R_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_transfer_sync( value, value, len);
	)
}
 68a:	0f 90       	pop	r0
 68c:	df 91       	pop	r29
 68e:	cf 91       	pop	r28
 690:	1f 91       	pop	r17
 692:	0f 91       	pop	r16
 694:	08 95       	ret

00000696 <lib_nRF24L01_TX_FIFO_is_full>:
// FIFO control
//-----------------------------------------------------------------------------

// returns true if there is a free TX FIFO available
bool lib_nRF24L01_TX_FIFO_is_full()
{
 696:	cf 93       	push	r28
 698:	df 93       	push	r29
 69a:	1f 92       	push	r1
 69c:	cd b7       	in	r28, 0x3d	; 61
 69e:	de b7       	in	r29, 0x3e	; 62
	uint8_t fifo_status;
	lib_nRF24L01_read_register( nRF_REG_FIFO_STATUS, &fifo_status, 1);
 6a0:	41 e0       	ldi	r20, 0x01	; 1
 6a2:	be 01       	movw	r22, r28
 6a4:	6f 5f       	subi	r22, 0xFF	; 255
 6a6:	7f 4f       	sbci	r23, 0xFF	; 255
 6a8:	87 e1       	ldi	r24, 0x17	; 23
 6aa:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	return ( fifo_status & nRF_REGBITMASK_FIFO_STATUS_TX_FULL );
 6ae:	89 81       	ldd	r24, Y+1	; 0x01
}
 6b0:	85 fb       	bst	r24, 5
 6b2:	88 27       	eor	r24, r24
 6b4:	80 f9       	bld	r24, 0
 6b6:	0f 90       	pop	r0
 6b8:	df 91       	pop	r29
 6ba:	cf 91       	pop	r28
 6bc:	08 95       	ret

000006be <lib_nRF24L01_write_TX_FIFO>:
// Writes packet data into TX FIFO.
// Returns false, if this fails because there is no free TX FIFO available, otherwise returns true.
// Note: - if the nRF24L01+ is in TX mode and CE is high, the data will be sent immediately.
//       - if the nRF24L01+ is in TX mode and CE is low , lib_nRF24L01_TriggerSingleTrans() (or lib_nRF24L01_start()) must be called to send the data
bool lib_nRF24L01_write_TX_FIFO( uint8_t * data, uint8_t len)
{
 6be:	0f 93       	push	r16
 6c0:	1f 93       	push	r17
 6c2:	cf 93       	push	r28
 6c4:	df 93       	push	r29
 6c6:	1f 92       	push	r1
 6c8:	cd b7       	in	r28, 0x3d	; 61
 6ca:	de b7       	in	r29, 0x3e	; 62
 6cc:	8c 01       	movw	r16, r24
	if ( lib_nRF24L01_TX_FIFO_is_full() )			// check for free FIFO
 6ce:	69 83       	std	Y+1, r22	; 0x01
 6d0:	0e 94 4b 03 	call	0x696	; 0x696 <lib_nRF24L01_TX_FIFO_is_full>
 6d4:	69 81       	ldd	r22, Y+1	; 0x01
 6d6:	81 11       	cpse	r24, r1
 6d8:	0c c0       	rjmp	.+24     	; 0x6f2 <lib_nRF24L01_write_TX_FIFO+0x34>
		return false;
	else
	{
		lib_nRF24L01_EXECUTE(
 6da:	5d 98       	cbi	0x0b, 5	; 11
 6dc:	80 ea       	ldi	r24, 0xA0	; 160
 6de:	69 83       	std	Y+1, r22	; 0x01
 6e0:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 6e4:	69 81       	ldd	r22, Y+1	; 0x01
 6e6:	c8 01       	movw	r24, r16
 6e8:	0e 94 3a 02 	call	0x474	; 0x474 <spi_transmit>
 6ec:	5d 9a       	sbi	0x0b, 5	; 11
 6ee:	81 e0       	ldi	r24, 0x01	; 1
 6f0:	01 c0       	rjmp	.+2      	; 0x6f4 <lib_nRF24L01_write_TX_FIFO+0x36>
// Note: - if the nRF24L01+ is in TX mode and CE is high, the data will be sent immediately.
//       - if the nRF24L01+ is in TX mode and CE is low , lib_nRF24L01_TriggerSingleTrans() (or lib_nRF24L01_start()) must be called to send the data
bool lib_nRF24L01_write_TX_FIFO( uint8_t * data, uint8_t len)
{
	if ( lib_nRF24L01_TX_FIFO_is_full() )			// check for free FIFO
		return false;
 6f2:	80 e0       	ldi	r24, 0x00	; 0
			spi_fast_shift( nRF_CMD_W_TX_PAYLOAD );
			spi_transmit_sync( data, len);
		)
		return true;
	}
}
 6f4:	0f 90       	pop	r0
 6f6:	df 91       	pop	r29
 6f8:	cf 91       	pop	r28
 6fa:	1f 91       	pop	r17
 6fc:	0f 91       	pop	r16
 6fe:	08 95       	ret

00000700 <lib_nRF24L01_TX_FIFO_is_empty>:
}


// returns true if TX_EMPTY bit in FIFO_STATUS register is set, false otherwise
bool lib_nRF24L01_TX_FIFO_is_empty()
{
 700:	cf 93       	push	r28
 702:	df 93       	push	r29
 704:	1f 92       	push	r1
 706:	cd b7       	in	r28, 0x3d	; 61
 708:	de b7       	in	r29, 0x3e	; 62
	uint8_t fifo_status;
	lib_nRF24L01_read_register( nRF_REG_FIFO_STATUS, &fifo_status, 1);
 70a:	41 e0       	ldi	r20, 0x01	; 1
 70c:	be 01       	movw	r22, r28
 70e:	6f 5f       	subi	r22, 0xFF	; 255
 710:	7f 4f       	sbci	r23, 0xFF	; 255
 712:	87 e1       	ldi	r24, 0x17	; 23
 714:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	return ( fifo_status & nRF_REGBITMASK_FIFO_STATUS_TX_EMPTY );
 718:	89 81       	ldd	r24, Y+1	; 0x01
}
 71a:	82 95       	swap	r24
 71c:	81 70       	andi	r24, 0x01	; 1
 71e:	0f 90       	pop	r0
 720:	df 91       	pop	r29
 722:	cf 91       	pop	r28
 724:	08 95       	ret

00000726 <lib_nRF24L01_send>:
// sending/transmitting data
//-----------------------------------------------------------------------------

// Simple implementation of sending a single data package
void lib_nRF24L01_send( uint8_t * data, uint8_t len)
{
 726:	1f 93       	push	r17
 728:	cf 93       	push	r28
 72a:	df 93       	push	r29
 72c:	ec 01       	movw	r28, r24
 72e:	16 2f       	mov	r17, r22
	if ( currentState & STATE_BITMASK_ACTIVE )			// in this case a packet written into an TX FIFO will be sent as soon as possible
 730:	80 91 02 01 	lds	r24, 0x0102
 734:	83 ff       	sbrs	r24, 3
 736:	07 c0       	rjmp	.+14     	; 0x746 <lib_nRF24L01_send+0x20>
	{
		while ( ! lib_nRF24L01_write_TX_FIFO( data, len) ) {}
 738:	61 2f       	mov	r22, r17
 73a:	ce 01       	movw	r24, r28
 73c:	0e 94 5f 03 	call	0x6be	; 0x6be <lib_nRF24L01_write_TX_FIFO>
 740:	88 23       	and	r24, r24
 742:	d1 f3       	breq	.-12     	; 0x738 <lib_nRF24L01_send+0x12>
 744:	10 c0       	rjmp	.+32     	; 0x766 <lib_nRF24L01_send+0x40>
	}
	else	// each packet has to be triggered separately
	{
		while ( ! lib_nRF24L01_TX_FIFO_is_empty() )		// first transmit all non empty FIFO slots
 746:	0e 94 80 03 	call	0x700	; 0x700 <lib_nRF24L01_TX_FIFO_is_empty>
 74a:	81 11       	cpse	r24, r1
 74c:	03 c0       	rjmp	.+6      	; 0x754 <lib_nRF24L01_send+0x2e>
		{
			lib_nRF24L01_TriggerSingleTrans();
 74e:	0e 94 8c 02 	call	0x518	; 0x518 <lib_nRF24L01_TriggerSingleTrans>
 752:	f9 cf       	rjmp	.-14     	; 0x746 <lib_nRF24L01_send+0x20>
		}
		lib_nRF24L01_write_TX_FIFO( data, len);
 754:	61 2f       	mov	r22, r17
 756:	ce 01       	movw	r24, r28
 758:	0e 94 5f 03 	call	0x6be	; 0x6be <lib_nRF24L01_write_TX_FIFO>
		lib_nRF24L01_TriggerSingleTrans();
	}
}
 75c:	df 91       	pop	r29
 75e:	cf 91       	pop	r28
 760:	1f 91       	pop	r17
		while ( ! lib_nRF24L01_TX_FIFO_is_empty() )		// first transmit all non empty FIFO slots
		{
			lib_nRF24L01_TriggerSingleTrans();
		}
		lib_nRF24L01_write_TX_FIFO( data, len);
		lib_nRF24L01_TriggerSingleTrans();
 762:	0c 94 8c 02 	jmp	0x518	; 0x518 <lib_nRF24L01_TriggerSingleTrans>
	}
}
 766:	df 91       	pop	r29
 768:	cf 91       	pop	r28
 76a:	1f 91       	pop	r17
 76c:	08 95       	ret

0000076e <lib_nRF24L01_RX_FIFO_is_empty>:
}


// returns true if RX_EMPTY bit in FIFO_STATUS register is set, false otherwise
bool lib_nRF24L01_RX_FIFO_is_empty()
{
 76e:	cf 93       	push	r28
 770:	df 93       	push	r29
 772:	1f 92       	push	r1
 774:	cd b7       	in	r28, 0x3d	; 61
 776:	de b7       	in	r29, 0x3e	; 62
	uint8_t fifo_status;
	lib_nRF24L01_read_register( nRF_REG_FIFO_STATUS, &fifo_status, 1);
 778:	41 e0       	ldi	r20, 0x01	; 1
 77a:	be 01       	movw	r22, r28
 77c:	6f 5f       	subi	r22, 0xFF	; 255
 77e:	7f 4f       	sbci	r23, 0xFF	; 255
 780:	87 e1       	ldi	r24, 0x17	; 23
 782:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	return ( fifo_status & nRF_REGBITMASK_FIFO_STATUS_RX_EMPTY );
 786:	89 81       	ldd	r24, Y+1	; 0x01
}
 788:	81 70       	andi	r24, 0x01	; 1
 78a:	0f 90       	pop	r0
 78c:	df 91       	pop	r29
 78e:	cf 91       	pop	r28
 790:	08 95       	ret

00000792 <lib_nRF24L01_get_arc_cnt>:
}


// Returns the number of Automatic Retransmitted data packets within Current transaction (an "Enhanced Shockburst" feature)
uint8_t lib_nRF24L01_get_arc_cnt()
{
 792:	cf 93       	push	r28
 794:	df 93       	push	r29
 796:	1f 92       	push	r1
 798:	cd b7       	in	r28, 0x3d	; 61
 79a:	de b7       	in	r29, 0x3e	; 62
	uint8_t observe_tx_data;
	lib_nRF24L01_read_register( nRF_REG_OBSERVE_TX, &observe_tx_data, 1);
 79c:	41 e0       	ldi	r20, 0x01	; 1
 79e:	be 01       	movw	r22, r28
 7a0:	6f 5f       	subi	r22, 0xFF	; 255
 7a2:	7f 4f       	sbci	r23, 0xFF	; 255
 7a4:	88 e0       	ldi	r24, 0x08	; 8
 7a6:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	return ( observe_tx_data & nRF_REGBITMASK_OBSERVE_TX_ARC_CNT );
 7aa:	89 81       	ldd	r24, Y+1	; 0x01
}
 7ac:	8f 70       	andi	r24, 0x0F	; 15
 7ae:	0f 90       	pop	r0
 7b0:	df 91       	pop	r29
 7b2:	cf 91       	pop	r28
 7b4:	08 95       	ret

000007b6 <lib_nRF24L01_get_plos_cnt>:


// Returns the number of Lost data packets since the last RF channel change (an "Enhanced Shockburst" feature)
uint8_t lib_nRF24L01_get_plos_cnt()
{
 7b6:	cf 93       	push	r28
 7b8:	df 93       	push	r29
 7ba:	1f 92       	push	r1
 7bc:	cd b7       	in	r28, 0x3d	; 61
 7be:	de b7       	in	r29, 0x3e	; 62
	uint8_t observe_tx_data;
	lib_nRF24L01_read_register( nRF_REG_OBSERVE_TX, &observe_tx_data, 1);
 7c0:	41 e0       	ldi	r20, 0x01	; 1
 7c2:	be 01       	movw	r22, r28
 7c4:	6f 5f       	subi	r22, 0xFF	; 255
 7c6:	7f 4f       	sbci	r23, 0xFF	; 255
 7c8:	88 e0       	ldi	r24, 0x08	; 8
 7ca:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	return ( (observe_tx_data & nRF_REGBITMASK_OBSERVE_TX_PLOS_CNT) >> 4 );
 7ce:	89 81       	ldd	r24, Y+1	; 0x01
}
 7d0:	82 95       	swap	r24
 7d2:	8f 70       	andi	r24, 0x0F	; 15
 7d4:	0f 90       	pop	r0
 7d6:	df 91       	pop	r29
 7d8:	cf 91       	pop	r28
 7da:	08 95       	ret

000007dc <lib_nRF24L01_write_register>:


// Writes an array of bytes into inte the nRF24L01-module registers.
// Returns value of nRF24L01 status register before any changes are done.
void lib_nRF24L01_write_register( uint8_t reg, uint8_t * value, uint8_t len)
{
 7dc:	0f 93       	push	r16
 7de:	1f 93       	push	r17
 7e0:	cf 93       	push	r28
 7e2:	df 93       	push	r29
 7e4:	1f 92       	push	r1
 7e6:	cd b7       	in	r28, 0x3d	; 61
 7e8:	de b7       	in	r29, 0x3e	; 62
 7ea:	8b 01       	movw	r16, r22
	lib_nRF24L01_EXECUTE(
 7ec:	5d 98       	cbi	0x0b, 5	; 11
 7ee:	8f 71       	andi	r24, 0x1F	; 31
 7f0:	80 62       	ori	r24, 0x20	; 32
 7f2:	49 83       	std	Y+1, r20	; 0x01
 7f4:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 7f8:	49 81       	ldd	r20, Y+1	; 0x01
 7fa:	64 2f       	mov	r22, r20
 7fc:	c8 01       	movw	r24, r16
 7fe:	0e 94 3a 02 	call	0x474	; 0x474 <spi_transmit>
 802:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_W_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_transmit_sync( value, len);
	)
}
 804:	0f 90       	pop	r0
 806:	df 91       	pop	r29
 808:	cf 91       	pop	r28
 80a:	1f 91       	pop	r17
 80c:	0f 91       	pop	r16
 80e:	08 95       	ret

00000810 <lib_nRF24L01_power_down>:
}


// Powers the nRF24L01+ down (saves power supply current)
void lib_nRF24L01_power_down()
{
 810:	cf 93       	push	r28
 812:	df 93       	push	r29
 814:	1f 92       	push	r1
 816:	cd b7       	in	r28, 0x3d	; 61
 818:	de b7       	in	r29, 0x3e	; 62
	unsigned char config;

	lib_nRF24L01_set_CE_low();		// stop active operation (recommended before powering down)
 81a:	0e 94 73 02 	call	0x4e6	; 0x4e6 <lib_nRF24L01_set_CE_low>
	
	lib_nRF24L01_read_register ( nRF_REG_CONFIG, &config, 1);
 81e:	41 e0       	ldi	r20, 0x01	; 1
 820:	be 01       	movw	r22, r28
 822:	6f 5f       	subi	r22, 0xFF	; 255
 824:	7f 4f       	sbci	r23, 0xFF	; 255
 826:	80 e0       	ldi	r24, 0x00	; 0
 828:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	config &= ~nRF_REGBITMASK_CONFIG_PWR_UP;
 82c:	89 81       	ldd	r24, Y+1	; 0x01
 82e:	8d 7f       	andi	r24, 0xFD	; 253
 830:	89 83       	std	Y+1, r24	; 0x01
	lib_nRF24L01_write_register( nRF_REG_CONFIG, &config, 1);
 832:	41 e0       	ldi	r20, 0x01	; 1
 834:	be 01       	movw	r22, r28
 836:	6f 5f       	subi	r22, 0xFF	; 255
 838:	7f 4f       	sbci	r23, 0xFF	; 255
 83a:	80 e0       	ldi	r24, 0x00	; 0
 83c:	0e 94 ee 03 	call	0x7dc	; 0x7dc <lib_nRF24L01_write_register>
	
	currentState &= ~STATE_BITMASK_PWR_UP;
 840:	80 91 02 01 	lds	r24, 0x0102
 844:	8d 7f       	andi	r24, 0xFD	; 253
 846:	80 93 02 01 	sts	0x0102, r24
}
 84a:	0f 90       	pop	r0
 84c:	df 91       	pop	r29
 84e:	cf 91       	pop	r28
 850:	08 95       	ret

00000852 <lib_nRF24L01_set_rx_addr.part.2>:
//		If an invalid address (greater than five) is supplied, the function does nothing.
//	addr_msbs
//		pointer to all bytes except the first one of the device address to be set
//	addr_lsb
//		first byte of the device address to be set
void lib_nRF24L01_set_rx_addr( uint8_t lib_nRF24L01_pipe_num, uint8_t groupID, uint8_t deviceID)
 852:	cf 93       	push	r28
 854:	df 93       	push	r29
 856:	00 d0       	rcall	.+0      	; 0x858 <lib_nRF24L01_set_rx_addr.part.2+0x6>
 858:	1f 92       	push	r1
 85a:	cd b7       	in	r28, 0x3d	; 61
 85c:	de b7       	in	r29, 0x3e	; 62
 85e:	98 2f       	mov	r25, r24
 860:	8a e0       	ldi	r24, 0x0A	; 10
 862:	89 0f       	add	r24, r25
{
	uint8_t address[lib_nRF24L01_ADDR_WIDTH];
	
	if ( lib_nRF24L01_pipe_num > 5 )
		return;									// §§ flag error status
	else if ( lib_nRF24L01_pipe_num < 2 )		// data pipes 0 and 1 are multi-byte address register values (byte count defined by SETUP_AW register)
 864:	92 30       	cpi	r25, 0x02	; 2
 866:	58 f4       	brcc	.+22     	; 0x87e <lib_nRF24L01_set_rx_addr.part.2+0x2c>
	{
		address[0] = deviceID;					// LSB first
 868:	49 83       	std	Y+1, r20	; 0x01
		address[1] = groupID;
 86a:	6a 83       	std	Y+2, r22	; 0x02
		address[2] = lib_nRF24L01_ADDR_MSB;
 86c:	92 e4       	ldi	r25, 0x42	; 66
 86e:	9b 83       	std	Y+3, r25	; 0x03
		lib_nRF24L01_write_register( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, address, lib_nRF24L01_ADDR_WIDTH);
 870:	43 e0       	ldi	r20, 0x03	; 3
 872:	be 01       	movw	r22, r28
 874:	6f 5f       	subi	r22, 0xFF	; 255
 876:	7f 4f       	sbci	r23, 0xFF	; 255
 878:	0e 94 ee 03 	call	0x7dc	; 0x7dc <lib_nRF24L01_write_register>
 87c:	03 c0       	rjmp	.+6      	; 0x884 <lib_nRF24L01_set_rx_addr.part.2+0x32>
	}
	else										// data pipes 2..5 get only the deviceID assigned, because their MSBytes are the same as of data pipe 1
	{
		lib_nRF24L01_set_regbyte( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, deviceID);
 87e:	64 2f       	mov	r22, r20
 880:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
	}

	
}
 884:	0f 90       	pop	r0
 886:	0f 90       	pop	r0
 888:	0f 90       	pop	r0
 88a:	df 91       	pop	r29
 88c:	cf 91       	pop	r28
 88e:	08 95       	ret

00000890 <lib_nRF24L01_set_regbits>:
	)
}


void lib_nRF24L01_set_regbits( uint8_t reg, uint8_t bitmask)
{
 890:	0f 93       	push	r16
 892:	1f 93       	push	r17
 894:	cf 93       	push	r28
 896:	df 93       	push	r29
 898:	1f 92       	push	r1
 89a:	cd b7       	in	r28, 0x3d	; 61
 89c:	de b7       	in	r29, 0x3e	; 62
 89e:	18 2f       	mov	r17, r24
 8a0:	06 2f       	mov	r16, r22
	unsigned char regvalue;

	lib_nRF24L01_read_register ( reg, &regvalue, 1);
 8a2:	41 e0       	ldi	r20, 0x01	; 1
 8a4:	be 01       	movw	r22, r28
 8a6:	6f 5f       	subi	r22, 0xFF	; 255
 8a8:	7f 4f       	sbci	r23, 0xFF	; 255
 8aa:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	regvalue |= bitmask;
 8ae:	99 81       	ldd	r25, Y+1	; 0x01
 8b0:	90 2b       	or	r25, r16
 8b2:	99 83       	std	Y+1, r25	; 0x01
	lib_nRF24L01_write_register( reg, &regvalue, 1);
 8b4:	41 e0       	ldi	r20, 0x01	; 1
 8b6:	be 01       	movw	r22, r28
 8b8:	6f 5f       	subi	r22, 0xFF	; 255
 8ba:	7f 4f       	sbci	r23, 0xFF	; 255
 8bc:	81 2f       	mov	r24, r17
 8be:	0e 94 ee 03 	call	0x7dc	; 0x7dc <lib_nRF24L01_write_register>
}
 8c2:	0f 90       	pop	r0
 8c4:	df 91       	pop	r29
 8c6:	cf 91       	pop	r28
 8c8:	1f 91       	pop	r17
 8ca:	0f 91       	pop	r16
 8cc:	08 95       	ret

000008ce <lib_nRF24L01_mask_IRQ>:
// 		nRF_REGBITMASK_CONFIG_MASK_TX_DS
// 		nRF_REGBITMASK_CONFIG_MASK_RX_DR
// 		nRF_REGBITMASK_CONFIG_MASK_MAX_RT
void lib_nRF24L01_mask_IRQ( uint8_t bitmask)
{
	lib_nRF24L01_set_regbits( nRF_REG_CONFIG, bitmask);
 8ce:	68 2f       	mov	r22, r24
 8d0:	80 e0       	ldi	r24, 0x00	; 0
 8d2:	0c 94 48 04 	jmp	0x890	; 0x890 <lib_nRF24L01_set_regbits>

000008d6 <lib_nRF24L01_clear_IRQ>:


// resets IRQ flag(s) in the STATUS register
void lib_nRF24L01_clear_IRQ( uint8_t bitmask)
{
	lib_nRF24L01_set_regbits( nRF_REG_STATUS, bitmask);		// IRQ flags are reset by writing a logical 1 to their bit position
 8d6:	68 2f       	mov	r22, r24
 8d8:	87 e0       	ldi	r24, 0x07	; 7
 8da:	0c 94 48 04 	jmp	0x890	; 0x890 <lib_nRF24L01_set_regbits>

000008de <lib_nRF24L01_unset_regbits>:
	lib_nRF24L01_write_register( reg, &regvalue, 1);
}


void lib_nRF24L01_unset_regbits( uint8_t reg, uint8_t bitmask)
{
 8de:	0f 93       	push	r16
 8e0:	1f 93       	push	r17
 8e2:	cf 93       	push	r28
 8e4:	df 93       	push	r29
 8e6:	1f 92       	push	r1
 8e8:	cd b7       	in	r28, 0x3d	; 61
 8ea:	de b7       	in	r29, 0x3e	; 62
 8ec:	18 2f       	mov	r17, r24
 8ee:	06 2f       	mov	r16, r22
	unsigned char regvalue;

	lib_nRF24L01_read_register ( reg, &regvalue, 1);
 8f0:	41 e0       	ldi	r20, 0x01	; 1
 8f2:	be 01       	movw	r22, r28
 8f4:	6f 5f       	subi	r22, 0xFF	; 255
 8f6:	7f 4f       	sbci	r23, 0xFF	; 255
 8f8:	0e 94 32 03 	call	0x664	; 0x664 <lib_nRF24L01_read_register>
	regvalue &= ~bitmask;
 8fc:	00 95       	com	r16
 8fe:	99 81       	ldd	r25, Y+1	; 0x01
 900:	90 23       	and	r25, r16
 902:	99 83       	std	Y+1, r25	; 0x01
	lib_nRF24L01_write_register( reg, &regvalue, 1);
 904:	41 e0       	ldi	r20, 0x01	; 1
 906:	be 01       	movw	r22, r28
 908:	6f 5f       	subi	r22, 0xFF	; 255
 90a:	7f 4f       	sbci	r23, 0xFF	; 255
 90c:	81 2f       	mov	r24, r17
 90e:	0e 94 ee 03 	call	0x7dc	; 0x7dc <lib_nRF24L01_write_register>
}
 912:	0f 90       	pop	r0
 914:	df 91       	pop	r29
 916:	cf 91       	pop	r28
 918:	1f 91       	pop	r17
 91a:	0f 91       	pop	r16
 91c:	08 95       	ret

0000091e <lib_nRF24L01_get_status>:

// return the value of the status register
uint8_t lib_nRF24L01_get_status()
{
	uint8_t status;
	lib_nRF24L01_EXECUTE(
 91e:	5d 98       	cbi	0x0b, 5	; 11
 920:	8f ef       	ldi	r24, 0xFF	; 255
 922:	0e 94 23 02 	call	0x446	; 0x446 <spi_transfer_byte>
 926:	5d 9a       	sbi	0x0b, 5	; 11
		status = spi_fast_shift( nRF_CMD_NOP);
	)
	return status;
}
 928:	08 95       	ret

0000092a <lib_nRF24L01_get_rx_pipe_num>:
// Returns the RX data pipe number of the data currently available in the RX-FIFO to be read out.
// Returns -1, if there is no data available (empty RX-FIFO).
int8_t lib_nRF24L01_get_rx_pipe_num()
{
	uint8_t lib_nRF24L01_pipe_num;
	lib_nRF24L01_pipe_num = ( lib_nRF24L01_get_status() & nRF_REGBITMASK_STATUS_RX_P_NO ) >> nRF_REGBITSHIFT_STATUS_RX_P_NO;
 92a:	0e 94 8f 04 	call	0x91e	; 0x91e <lib_nRF24L01_get_status>
 92e:	8e 70       	andi	r24, 0x0E	; 14
 930:	90 e0       	ldi	r25, 0x00	; 0
 932:	95 95       	asr	r25
 934:	87 95       	ror	r24
	if ( lib_nRF24L01_pipe_num <= 5 )
 936:	86 30       	cpi	r24, 0x06	; 6
 938:	08 f0       	brcs	.+2      	; 0x93c <lib_nRF24L01_get_rx_pipe_num+0x12>
		return lib_nRF24L01_pipe_num;
	else	// lib_nRF24L01_pipe_num == ( nRF_REGVAL_STATUS_RX_P_NO_FIFO_EMPTY >> nRF_REGBITSHIFT_STATUS_RX_P_NO )
		return -1;
 93a:	8f ef       	ldi	r24, 0xFF	; 255
}
 93c:	08 95       	ret

0000093e <lib_nRF24L01_handle_interrupt>:
//				if ( lib_nRF24L01_IRQ_scheduled ) lib_nRF24L01_handle_interrupt();
//				...;
//			}
// If another/more functionality is needed by the application, the application needs to define its own interrupt handling function.
void lib_nRF24L01_handle_interrupt( void)
{
 93e:	cf 93       	push	r28
	uint8_t status = lib_nRF24L01_get_status();
 940:	0e 94 8f 04 	call	0x91e	; 0x91e <lib_nRF24L01_get_status>
 944:	c8 2f       	mov	r28, r24

	// packet successfully sent
	if ( status & nRF_REGBITMASK_STATUS_TX_DS )													
 946:	85 ff       	sbrs	r24, 5
 948:	03 c0       	rjmp	.+6      	; 0x950 <lib_nRF24L01_handle_interrupt+0x12>
	{
#ifdef DEBUG
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
#endif
		// no need to do anything but to reset the IRQ flag
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_TX_DS);
 94a:	80 e2       	ldi	r24, 0x20	; 32
 94c:	0e 94 6b 04 	call	0x8d6	; 0x8d6 <lib_nRF24L01_clear_IRQ>
	}

	// packet received
	if ( status & nRF_REGBITMASK_STATUS_RX_DR )														
 950:	c6 fd       	sbrc	r28, 6
 952:	08 c0       	rjmp	.+16     	; 0x964 <lib_nRF24L01_handle_interrupt+0x26>
		while ( lib_nRF24L01_get_regbyte( nRF_REG_FIFO_STATUS) & nRF_REGBITMASK_STATUS_RX_DR )
			lib_nRF24L01_flush_RX_FIFO();
	}

	// maximum automatic retransmits reached -> packet not successfully sent
	if ( status & nRF_REGBITMASK_STATUS_MAX_RT )
 954:	c4 ff       	sbrs	r28, 4
 956:	1d c0       	rjmp	.+58     	; 0x992 <lib_nRF24L01_handle_interrupt+0x54>
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
#endif
		// keep your mind free and just forget that this happened
		// § alternatively, CE could be toggled in order to trigger another transmission cycle
		lib_nRF24L01_flush_TX_FIFO();
 958:	0e 94 5c 02 	call	0x4b8	; 0x4b8 <lib_nRF24L01_flush_TX_FIFO>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_MAX_RT);
 95c:	80 e1       	ldi	r24, 0x10	; 16
 95e:	0e 94 6b 04 	call	0x8d6	; 0x8d6 <lib_nRF24L01_clear_IRQ>
 962:	17 c0       	rjmp	.+46     	; 0x992 <lib_nRF24L01_handle_interrupt+0x54>
	{
#ifdef DEBUG
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
#endif
		lib_nRF24L01_pipe_num = lib_nRF24L01_get_rx_pipe_num();		// store source and data in static variables
 964:	0e 94 95 04 	call	0x92a	; 0x92a <lib_nRF24L01_get_rx_pipe_num>
 968:	80 93 2b 01 	sts	0x012B, r24
		lib_nRF24L01_get_data( lib_nRF24L01_RX_data, nRF24L01_MAX_RX_PAYLOAD_LEN);		// § overwrites RX-data even if the main app has not processed it yet
 96c:	60 e2       	ldi	r22, 0x20	; 32
 96e:	8b e0       	ldi	r24, 0x0B	; 11
 970:	91 e0       	ldi	r25, 0x01	; 1
 972:	0e 94 05 03 	call	0x60a	; 0x60a <lib_nRF24L01_get_data>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_RX_DR);
 976:	80 e4       	ldi	r24, 0x40	; 64
 978:	0e 94 6b 04 	call	0x8d6	; 0x8d6 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_newDataAvailable = true;
 97c:	81 e0       	ldi	r24, 0x01	; 1
 97e:	80 93 2c 01 	sts	0x012C, r24
		// discard any other data received
		// §§ of course, the data should be stored as well, if needed
		while ( lib_nRF24L01_get_regbyte( nRF_REG_FIFO_STATUS) & nRF_REGBITMASK_STATUS_RX_DR )
 982:	87 e1       	ldi	r24, 0x17	; 23
 984:	0e 94 b2 02 	call	0x564	; 0x564 <lib_nRF24L01_get_regbyte>
 988:	86 ff       	sbrs	r24, 6
 98a:	e4 cf       	rjmp	.-56     	; 0x954 <lib_nRF24L01_handle_interrupt+0x16>
			lib_nRF24L01_flush_RX_FIFO();
 98c:	0e 94 62 02 	call	0x4c4	; 0x4c4 <lib_nRF24L01_flush_RX_FIFO>
 990:	f8 cf       	rjmp	.-16     	; 0x982 <lib_nRF24L01_handle_interrupt+0x44>
		// § alternatively, CE could be toggled in order to trigger another transmission cycle
		lib_nRF24L01_flush_TX_FIFO();
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_MAX_RT);
	}
	
	lib_nRF24L01_IRQ_scheduled = false;								// pretend all is done
 992:	10 92 2d 01 	sts	0x012D, r1
}
 996:	cf 91       	pop	r28
 998:	08 95       	ret

0000099a <lib_nRF24L01_data_ready>:


// Checks if RX data is available for reading
bool lib_nRF24L01_data_ready()
{
	return lib_nRF24L01_get_status() & nRF_REGBITMASK_STATUS_RX_DR;
 99a:	0e 94 8f 04 	call	0x91e	; 0x91e <lib_nRF24L01_get_status>
}
 99e:	86 fb       	bst	r24, 6
 9a0:	88 27       	eor	r24, r24
 9a2:	80 f9       	bld	r24, 0
 9a4:	08 95       	ret

000009a6 <lib_nRF24L01_set_tx_addr>:
//	addr_msbs
//		pointer to all bytes except the first one of the device address to be set
//	addr_lsb
//		first byte of the device address to be set
void lib_nRF24L01_set_tx_addr( uint8_t groupID, uint8_t deviceID)
{
 9a6:	cf 93       	push	r28
 9a8:	df 93       	push	r29
 9aa:	00 d0       	rcall	.+0      	; 0x9ac <lib_nRF24L01_set_tx_addr+0x6>
 9ac:	1f 92       	push	r1
 9ae:	cd b7       	in	r28, 0x3d	; 61
 9b0:	de b7       	in	r29, 0x3e	; 62
	uint8_t address[lib_nRF24L01_ADDR_WIDTH];

	address[0] = deviceID;						// LSB first
 9b2:	69 83       	std	Y+1, r22	; 0x01
	address[1] = groupID;
 9b4:	8a 83       	std	Y+2, r24	; 0x02
	address[2] = lib_nRF24L01_ADDR_MSB;
 9b6:	82 e4       	ldi	r24, 0x42	; 66
 9b8:	8b 83       	std	Y+3, r24	; 0x03

	lib_nRF24L01_write_register( nRF_REG_TX_ADDR, address, lib_nRF24L01_ADDR_WIDTH);
 9ba:	43 e0       	ldi	r20, 0x03	; 3
 9bc:	be 01       	movw	r22, r28
 9be:	6f 5f       	subi	r22, 0xFF	; 255
 9c0:	7f 4f       	sbci	r23, 0xFF	; 255
 9c2:	80 e1       	ldi	r24, 0x10	; 16
 9c4:	0e 94 ee 03 	call	0x7dc	; 0x7dc <lib_nRF24L01_write_register>
}
 9c8:	0f 90       	pop	r0
 9ca:	0f 90       	pop	r0
 9cc:	0f 90       	pop	r0
 9ce:	df 91       	pop	r29
 9d0:	cf 91       	pop	r28
 9d2:	08 95       	ret

000009d4 <lib_nRF24L01_init_nRF24L01>:
//		mode		lib_nRF24L01_TXmode | lib_nRF24L01_RXmode
// 		groupID 	the middle byte of the address of the nRF24L01+. This lib uses this byte as common address part of a multiceiver-group.
// 		deviceID 	the LSByte of the address of the nRF24L01+. This lib uses default values from 1...6 for the transmitters of a multiceiver-group.
// 		rf_channel	RF frequency channel to use: F(RF) = 2400 + x [MHz], where x = 0..125
void lib_nRF24L01_init_nRF24L01( uint8_t mode, uint8_t groupID, uint8_t deviceID, uint8_t rf_channel)
{
 9d4:	ff 92       	push	r15
 9d6:	0f 93       	push	r16
 9d8:	1f 93       	push	r17
 9da:	cf 93       	push	r28
 9dc:	df 93       	push	r29
 9de:	1f 92       	push	r1
 9e0:	cd b7       	in	r28, 0x3d	; 61
 9e2:	de b7       	in	r29, 0x3e	; 62
 9e4:	18 2f       	mov	r17, r24
 9e6:	06 2f       	mov	r16, r22
 9e8:	f4 2e       	mov	r15, r20
	// the nRF24L01+ power on reset procedure needs 100ms after operating voltage is supplied
	if ( ! (currentState & STATE_BITMASK_INIT  ) )
 9ea:	80 91 02 01 	lds	r24, 0x0102
 9ee:	80 fd       	sbrc	r24, 0
 9f0:	09 c0       	rjmp	.+18     	; 0xa04 <lib_nRF24L01_init_nRF24L01+0x30>
 9f2:	3f ef       	ldi	r19, 0xFF	; 255
 9f4:	81 ee       	ldi	r24, 0xE1	; 225
 9f6:	94 e0       	ldi	r25, 0x04	; 4
 9f8:	31 50       	subi	r19, 0x01	; 1
 9fa:	80 40       	sbci	r24, 0x00	; 0
 9fc:	90 40       	sbci	r25, 0x00	; 0
 9fe:	e1 f7       	brne	.-8      	; 0x9f8 <lib_nRF24L01_init_nRF24L01+0x24>
 a00:	00 c0       	rjmp	.+0      	; 0xa02 <lib_nRF24L01_init_nRF24L01+0x2e>
 a02:	00 00       	nop
		_delay_us( nRF24L01_DELAY_POWERON_RESET);

	if (   (currentState & STATE_BITMASK_PWR_UP) )
 a04:	80 91 02 01 	lds	r24, 0x0102
 a08:	81 ff       	sbrs	r24, 1
 a0a:	11 c0       	rjmp	.+34     	; 0xa2e <lib_nRF24L01_init_nRF24L01+0x5a>
	{
		// flush all data pipes, reset all interrupt flags (IRQ-pin), then go down
		lib_nRF24L01_flush_TX_FIFO();
 a0c:	29 83       	std	Y+1, r18	; 0x01
 a0e:	0e 94 5c 02 	call	0x4b8	; 0x4b8 <lib_nRF24L01_flush_TX_FIFO>
		lib_nRF24L01_flush_RX_FIFO();
 a12:	0e 94 62 02 	call	0x4c4	; 0x4c4 <lib_nRF24L01_flush_RX_FIFO>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_TX_DS);
 a16:	80 e2       	ldi	r24, 0x20	; 32
 a18:	0e 94 6b 04 	call	0x8d6	; 0x8d6 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_RX_DR);
 a1c:	80 e4       	ldi	r24, 0x40	; 64
 a1e:	0e 94 6b 04 	call	0x8d6	; 0x8d6 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_MAX_RT);
 a22:	80 e1       	ldi	r24, 0x10	; 16
 a24:	0e 94 6b 04 	call	0x8d6	; 0x8d6 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_power_down();
 a28:	0e 94 08 04 	call	0x810	; 0x810 <lib_nRF24L01_power_down>
 a2c:	29 81       	ldd	r18, Y+1	; 0x01
	}

	// Set RF channel
	lib_nRF24L01_set_regbyte( nRF_REG_RF_CH, rf_channel);
 a2e:	62 2f       	mov	r22, r18
 a30:	85 e0       	ldi	r24, 0x05	; 5
 a32:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
	// Set data speed & Output Power configured in lib_nRF24L01.h
	lib_nRF24L01_set_regbyte( nRF_REG_RF_SETUP, lib_nRF24L01_RF_SETUP);
 a36:	66 e2       	ldi	r22, 0x26	; 38
 a38:	86 e0       	ldi	r24, 0x06	; 6
 a3a:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>

	// Set Device Address Width
	lib_nRF24L01_set_regbyte( nRF_REG_SETUP_AW, nRF_REGBITVAL_SETUP_AW_3BYTES);
 a3e:	61 e0       	ldi	r22, 0x01	; 1
 a40:	83 e0       	ldi	r24, 0x03	; 3
 a42:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
	
	// Set device addresses for a "multiceiver group" (a star topology consisting of 1 receiver and up to 6 transmitters) with auto acknowledge
	if ( mode == lib_nRF24L01_TXmode )
 a46:	11 30       	cpi	r17, 0x01	; 1
 a48:	41 f5       	brne	.+80     	; 0xa9a <lib_nRF24L01_init_nRF24L01+0xc6>
	{
		// Set Device Address (which identifies the transmitter)
		lib_nRF24L01_set_tx_addr( groupID, deviceID);
 a4a:	6f 2d       	mov	r22, r15
 a4c:	80 2f       	mov	r24, r16
 a4e:	0e 94 d3 04 	call	0x9a6	; 0x9a6 <lib_nRF24L01_set_tx_addr>
		// Enable only RX data pipe 0 for receiving data (to receive acknowledge-packets from a listening receiver)
		lib_nRF24L01_set_regbyte( nRF_REG_EN_RXADDR, nRF_REGBITMASK_EN_RXADDR_ERX_P0);
 a52:	61 e0       	ldi	r22, 0x01	; 1
 a54:	82 e0       	ldi	r24, 0x02	; 2
 a56:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 a5a:	4f 2d       	mov	r20, r15
 a5c:	60 2f       	mov	r22, r16
 a5e:	80 e0       	ldi	r24, 0x00	; 0
 a60:	0e 94 29 04 	call	0x852	; 0x852 <lib_nRF24L01_set_rx_addr.part.2>
 a64:	4f ef       	ldi	r20, 0xFF	; 255
 a66:	6f ef       	ldi	r22, 0xFF	; 255
 a68:	81 e0       	ldi	r24, 0x01	; 1
 a6a:	0e 94 29 04 	call	0x852	; 0x852 <lib_nRF24L01_set_rx_addr.part.2>
		address[2] = lib_nRF24L01_ADDR_MSB;
		lib_nRF24L01_write_register( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, address, lib_nRF24L01_ADDR_WIDTH);
	}
	else										// data pipes 2..5 get only the deviceID assigned, because their MSBytes are the same as of data pipe 1
	{
		lib_nRF24L01_set_regbyte( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, deviceID);
 a6e:	6f ef       	ldi	r22, 0xFF	; 255
 a70:	8c e0       	ldi	r24, 0x0C	; 12
 a72:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 a76:	6f ef       	ldi	r22, 0xFF	; 255
 a78:	8d e0       	ldi	r24, 0x0D	; 13
 a7a:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 a7e:	6f ef       	ldi	r22, 0xFF	; 255
 a80:	8e e0       	ldi	r24, 0x0E	; 14
 a82:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 a86:	6f ef       	ldi	r22, 0xFF	; 255
 a88:	8f e0       	ldi	r24, 0x0F	; 15
 a8a:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
	// ... Automatic Retransmission
	//     Note 1: use nRF_REG_SETUP_RETR ARD setting faster than 500us with caution: read note (d) at the end of the Register Map Table (page 60 of manual)!
	//     Note 2: § in order to avoid repeated transmission collisions, ensure different values for each device working on the same RF-channel
	if ( mode == lib_nRF24L01_TXmode )
	{
		uint8_t delay = (0x10 * (1+deviceID)) & nRF_REGBITMASK_SETUP_RETR_ARD;		// see nRF_REGVAL_SETUP_RETR_ARD_*-constants
 a8e:	6f 2d       	mov	r22, r15
 a90:	62 95       	swap	r22
 a92:	60 7f       	andi	r22, 0xF0	; 240
 a94:	60 5f       	subi	r22, 0xF0	; 240
		lib_nRF24L01_set_regbyte( nRF_REG_SETUP_RETR, (delay | nRF_REGVAL_SETUP_RETR_ARC_15) );
 a96:	6f 60       	ori	r22, 0x0F	; 15
 a98:	28 c0       	rjmp	.+80     	; 0xaea <lib_nRF24L01_init_nRF24L01+0x116>
	}
	else	// i.e. mode == lib_nRF24L01_RXmode (multiceiver)
	{
		// In order to avoid address conflicts which could occur when the PRX is switched to TX mode on the fly,
		// the Device Address is set even in RX-mode
		lib_nRF24L01_set_tx_addr(    groupID, deviceID > 6 ? deviceID : 0);		// ensure the deviceID does not collide with one of the transmitters of the same group
 a9a:	e6 e0       	ldi	r30, 0x06	; 6
 a9c:	ef 15       	cp	r30, r15
 a9e:	10 f0       	brcs	.+4      	; 0xaa4 <lib_nRF24L01_init_nRF24L01+0xd0>
 aa0:	60 e0       	ldi	r22, 0x00	; 0
 aa2:	01 c0       	rjmp	.+2      	; 0xaa6 <lib_nRF24L01_init_nRF24L01+0xd2>
 aa4:	6f 2d       	mov	r22, r15
 aa6:	80 2f       	mov	r24, r16
 aa8:	0e 94 d3 04 	call	0x9a6	; 0x9a6 <lib_nRF24L01_set_tx_addr>
		// Enable all RX data pipe addresses for receiving data
		lib_nRF24L01_set_regbyte( nRF_REG_EN_RXADDR, nRF_REGBITMASK_EN_RXADDR_ERX_ALL);
 aac:	6f e3       	ldi	r22, 0x3F	; 63
 aae:	82 e0       	ldi	r24, 0x02	; 2
 ab0:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 ab4:	41 e0       	ldi	r20, 0x01	; 1
 ab6:	60 2f       	mov	r22, r16
 ab8:	80 e0       	ldi	r24, 0x00	; 0
 aba:	0e 94 29 04 	call	0x852	; 0x852 <lib_nRF24L01_set_rx_addr.part.2>
 abe:	42 e0       	ldi	r20, 0x02	; 2
 ac0:	60 2f       	mov	r22, r16
 ac2:	81 e0       	ldi	r24, 0x01	; 1
 ac4:	0e 94 29 04 	call	0x852	; 0x852 <lib_nRF24L01_set_rx_addr.part.2>
		address[2] = lib_nRF24L01_ADDR_MSB;
		lib_nRF24L01_write_register( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, address, lib_nRF24L01_ADDR_WIDTH);
	}
	else										// data pipes 2..5 get only the deviceID assigned, because their MSBytes are the same as of data pipe 1
	{
		lib_nRF24L01_set_regbyte( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, deviceID);
 ac8:	63 e0       	ldi	r22, 0x03	; 3
 aca:	8c e0       	ldi	r24, 0x0C	; 12
 acc:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 ad0:	64 e0       	ldi	r22, 0x04	; 4
 ad2:	8d e0       	ldi	r24, 0x0D	; 13
 ad4:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 ad8:	65 e0       	ldi	r22, 0x05	; 5
 ada:	8e e0       	ldi	r24, 0x0E	; 14
 adc:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
 ae0:	66 e0       	ldi	r22, 0x06	; 6
 ae2:	8f e0       	ldi	r24, 0x0F	; 15
 ae4:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
		uint8_t delay = (0x10 * (1+deviceID)) & nRF_REGBITMASK_SETUP_RETR_ARD;		// see nRF_REGVAL_SETUP_RETR_ARD_*-constants
		lib_nRF24L01_set_regbyte( nRF_REG_SETUP_RETR, (delay | nRF_REGVAL_SETUP_RETR_ARC_15) );
	}
	else
	{
		lib_nRF24L01_set_regbyte( nRF_REG_SETUP_RETR, (nRF_REGVAL_SETUP_RETR_ARD_500 | nRF_REGVAL_SETUP_RETR_ARC_15) );
 ae8:	6f e1       	ldi	r22, 0x1F	; 31
 aea:	84 e0       	ldi	r24, 0x04	; 4
 aec:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
	}
	// ... Dynamic Payload Length as well as Automatic Acknowledgement Payloads
	lib_nRF24L01_set_regbyte( nRF_REG_FEATURE,   nRF_REGBITMASK_FEATURE_EN_DPL			// enables Dynamic Payload Length
 af0:	67 e0       	ldi	r22, 0x07	; 7
 af2:	8d e1       	ldi	r24, 0x1D	; 29
 af4:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
											   | nRF_REGBITMASK_FEATURE_EN_DYN_ACK		// enables use of nRF_CMD_W_TX_PAYLOAD_NOACK command
											   | nRF_REGBITMASK_FEATURE_EN_ACK_PAY		// enables "Acknowledge Payloads"
							);
	// ... enable Automatic Acknowledgement for all data pipes
	lib_nRF24L01_set_regbyte( nRF_REG_EN_AA, nRF_REGBITMASK_EN_AA_ENAA_ALL);
 af8:	6f e3       	ldi	r22, 0x3F	; 63
 afa:	81 e0       	ldi	r24, 0x01	; 1
 afc:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>
	// ... enable Dynamic Payload Length for all data pipes
	lib_nRF24L01_set_regbyte( nRF_REG_DYNPD, nRF_REGBITMASK_DYNPD_ALL);
 b00:	6f e3       	ldi	r22, 0x3F	; 63
 b02:	8c e1       	ldi	r24, 0x1C	; 28
 b04:	0e 94 c8 02 	call	0x590	; 0x590 <lib_nRF24L01_set_regbyte>

	currentState = STATE_BITMASK_INIT;						// initialised, powered down
 b08:	81 e0       	ldi	r24, 0x01	; 1
 b0a:	80 93 02 01 	sts	0x0102, r24
}
 b0e:	0f 90       	pop	r0
 b10:	df 91       	pop	r29
 b12:	cf 91       	pop	r28
 b14:	1f 91       	pop	r17
 b16:	0f 91       	pop	r16
 b18:	ff 90       	pop	r15
 b1a:	08 95       	ret

00000b1c <lib_nRF24L01_init>:
//-----------------------------------------------------------------------------
// initialising
//-----------------------------------------------------------------------------

void lib_nRF24L01_init( uint8_t mode, uint8_t groupID, uint8_t deviceID, uint8_t rf_channel)
{
 b1c:	cf 93       	push	r28
 b1e:	df 93       	push	r29
 b20:	00 d0       	rcall	.+0      	; 0xb22 <lib_nRF24L01_init+0x6>
 b22:	00 d0       	rcall	.+0      	; 0xb24 <lib_nRF24L01_init+0x8>
 b24:	cd b7       	in	r28, 0x3d	; 61
 b26:	de b7       	in	r29, 0x3e	; 62
	lib_nRF24L01_init_MCU();
 b28:	2c 83       	std	Y+4, r18	; 0x04
 b2a:	4b 83       	std	Y+3, r20	; 0x03
 b2c:	6a 83       	std	Y+2, r22	; 0x02
 b2e:	89 83       	std	Y+1, r24	; 0x01
 b30:	0e 94 7a 02 	call	0x4f4	; 0x4f4 <lib_nRF24L01_init_MCU>
	lib_nRF24L01_init_nRF24L01( mode, groupID, deviceID, rf_channel);
 b34:	2c 81       	ldd	r18, Y+4	; 0x04
 b36:	4b 81       	ldd	r20, Y+3	; 0x03
 b38:	6a 81       	ldd	r22, Y+2	; 0x02
 b3a:	89 81       	ldd	r24, Y+1	; 0x01
 b3c:	0e 94 ea 04 	call	0x9d4	; 0x9d4 <lib_nRF24L01_init_nRF24L01>
	lib_nRF24L01_IRQ_scheduled = false;
 b40:	10 92 2d 01 	sts	0x012D, r1
}
 b44:	0f 90       	pop	r0
 b46:	0f 90       	pop	r0
 b48:	0f 90       	pop	r0
 b4a:	0f 90       	pop	r0
 b4c:	df 91       	pop	r29
 b4e:	cf 91       	pop	r28
 b50:	08 95       	ret

00000b52 <lib_nRF24L01_set_rx_addr>:
//		first byte of the device address to be set
void lib_nRF24L01_set_rx_addr( uint8_t lib_nRF24L01_pipe_num, uint8_t groupID, uint8_t deviceID)
{
	uint8_t address[lib_nRF24L01_ADDR_WIDTH];
	
	if ( lib_nRF24L01_pipe_num > 5 )
 b52:	86 30       	cpi	r24, 0x06	; 6
 b54:	10 f4       	brcc	.+4      	; 0xb5a <lib_nRF24L01_set_rx_addr+0x8>
 b56:	0c 94 29 04 	jmp	0x852	; 0x852 <lib_nRF24L01_set_rx_addr.part.2>
 b5a:	08 95       	ret

00000b5c <main>:


int main( void)
{
 b5c:	cf 93       	push	r28
 b5e:	df 93       	push	r29
 b60:	00 d0       	rcall	.+0      	; 0xb62 <main+0x6>
 b62:	cd b7       	in	r28, 0x3d	; 61
 b64:	de b7       	in	r29, 0x3e	; 62
	uint16_t wdt_counter = 0;										// counts the number of times the MCU awakes by a watchdog interrupt
	uint8_t  sensordata[2];											// [0] humidity, [1] temperature

	// LED port pin
	PORTC &= ~(1<<PC3);
 b66:	43 98       	cbi	0x08, 3	; 8
	DDRC  |=  (1<<PC3);
 b68:	3b 9a       	sbi	0x07, 3	; 7

	// transmitter module
	lib_nRF24L01_init( lib_nRF24L01_TXmode, 69, 1, 42);				// mode, groupID (arbitrary), deviceID (1..6), rf_channel (0..125)
 b6a:	2a e2       	ldi	r18, 0x2A	; 42
 b6c:	41 e0       	ldi	r20, 0x01	; 1
 b6e:	65 e4       	ldi	r22, 0x45	; 69
 b70:	81 e0       	ldi	r24, 0x01	; 1
 b72:	0e 94 8e 05 	call	0xb1c	; 0xb1c <lib_nRF24L01_init>
	lib_nRF24L01_invoke_TX_mode();									// note: starts the RF oscillator but not the RF power amp
 b76:	0e 94 f0 02 	call	0x5e0	; 0x5e0 <lib_nRF24L01_invoke_TX_mode>

	// watchdog sleep-timer
	setupWatchdogInterrupt();
 b7a:	0e 94 53 00 	call	0xa6	; 0xa6 <setupWatchdogInterrupt>
	set_sleep_mode( SLEEP_MODE_PWR_DOWN);
 b7e:	83 b7       	in	r24, 0x33	; 51
 b80:	81 7f       	andi	r24, 0xF1	; 241
 b82:	84 60       	ori	r24, 0x04	; 4
 b84:	83 bf       	out	0x33, r24	; 51
	uint8_t xxx = 0;
 b86:	10 e0       	ldi	r17, 0x00	; 0
		{
			wdt_counter = ACTION_INTERVAL >= WDT_INTERVAL ? ACTION_INTERVAL / WDT_INTERVAL - 1
														  : 0;

			// flash LED
			PORTC |=  (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3);
 b88:	43 9a       	sbi	0x08, 3	; 8
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 b8a:	8f e1       	ldi	r24, 0x1F	; 31
 b8c:	9e e4       	ldi	r25, 0x4E	; 78
 b8e:	01 97       	sbiw	r24, 0x01	; 1
 b90:	f1 f7       	brne	.-4      	; 0xb8e <main+0x32>
 b92:	00 c0       	rjmp	.+0      	; 0xb94 <main+0x38>
 b94:	00 00       	nop
 b96:	43 98       	cbi	0x08, 3	; 8
			
			// measurement
			acquire_DHT();											// note: the DHT11 should not be acquired a) within 1s after power on and b) more then once per second
 b98:	0e 94 ba 00 	call	0x174	; 0x174 <acquire_DHT>
			sensordata[0] = get_humidity();
 b9c:	0e 94 04 02 	call	0x408	; 0x408 <get_humidity>
 ba0:	89 83       	std	Y+1, r24	; 0x01
			sensordata[1] = get_temperature();
 ba2:	0e 94 0d 02 	call	0x41a	; 0x41a <get_temperature>
			sensordata[1] = xxx++;
 ba6:	01 e0       	ldi	r16, 0x01	; 1
 ba8:	01 0f       	add	r16, r17
 baa:	1a 83       	std	Y+2, r17	; 0x02
			
			// send data
			if ( lib_nRF24L01_IRQ_scheduled )
 bac:	80 91 2d 01 	lds	r24, 0x012D
 bb0:	81 11       	cpse	r24, r1
				lib_nRF24L01_handle_interrupt();
 bb2:	0e 94 9f 04 	call	0x93e	; 0x93e <lib_nRF24L01_handle_interrupt>
			lib_nRF24L01_send( sensordata, 2);
 bb6:	62 e0       	ldi	r22, 0x02	; 2
 bb8:	ce 01       	movw	r24, r28
 bba:	01 96       	adiw	r24, 0x01	; 1
 bbc:	0e 94 93 03 	call	0x726	; 0x726 <lib_nRF24L01_send>
		}

		// goto sleep mode with minimal current draw, after watchdog awakening services are switched on again
		lib_nRF24L01_power_down();
 bc0:	0e 94 08 04 	call	0x810	; 0x810 <lib_nRF24L01_power_down>
		spi_stop();
 bc4:	0e 94 1f 02 	call	0x43e	; 0x43e <spi_stop>
		lib_nRF24L01_start();										// mode, groupID (arbitrary), deviceID (1..6), rf_channel (0..125)
 bc8:	0e 94 99 02 	call	0x532	; 0x532 <lib_nRF24L01_start>
		sei();														// ensure interrupts are enabled, otherwise the MCU will go into eternal sleep
 bcc:	78 94       	sei
		sleep_mode();												// go to sleep now and wait for watchdog interrupt
 bce:	83 b7       	in	r24, 0x33	; 51
 bd0:	81 60       	ori	r24, 0x01	; 1
 bd2:	83 bf       	out	0x33, r24	; 51
 bd4:	88 95       	sleep
 bd6:	83 b7       	in	r24, 0x33	; 51
 bd8:	8e 7f       	andi	r24, 0xFE	; 254
 bda:	83 bf       	out	0x33, r24	; 51
		spi_init();													// §§ if lib_nRF24L01_init() selects special SPI properties, just calling spi_init() here will not be enough
 bdc:	0e 94 16 02 	call	0x42c	; 0x42c <spi_init>
		lib_nRF24L01_invoke_TX_mode();
 be0:	0e 94 f0 02 	call	0x5e0	; 0x5e0 <lib_nRF24L01_invoke_TX_mode>
	}
 be4:	10 2f       	mov	r17, r16
 be6:	d0 cf       	rjmp	.-96     	; 0xb88 <main+0x2c>

00000be8 <__divmodsi4>:
 be8:	05 2e       	mov	r0, r21
 bea:	97 fb       	bst	r25, 7
 bec:	1e f4       	brtc	.+6      	; 0xbf4 <__divmodsi4+0xc>
 bee:	00 94       	com	r0
 bf0:	0e 94 0b 06 	call	0xc16	; 0xc16 <__negsi2>
 bf4:	57 fd       	sbrc	r21, 7
 bf6:	07 d0       	rcall	.+14     	; 0xc06 <__divmodsi4_neg2>
 bf8:	0e 94 22 06 	call	0xc44	; 0xc44 <__udivmodsi4>
 bfc:	07 fc       	sbrc	r0, 7
 bfe:	03 d0       	rcall	.+6      	; 0xc06 <__divmodsi4_neg2>
 c00:	4e f4       	brtc	.+18     	; 0xc14 <__divmodsi4_exit>
 c02:	0c 94 0b 06 	jmp	0xc16	; 0xc16 <__negsi2>

00000c06 <__divmodsi4_neg2>:
 c06:	50 95       	com	r21
 c08:	40 95       	com	r20
 c0a:	30 95       	com	r19
 c0c:	21 95       	neg	r18
 c0e:	3f 4f       	sbci	r19, 0xFF	; 255
 c10:	4f 4f       	sbci	r20, 0xFF	; 255
 c12:	5f 4f       	sbci	r21, 0xFF	; 255

00000c14 <__divmodsi4_exit>:
 c14:	08 95       	ret

00000c16 <__negsi2>:
 c16:	90 95       	com	r25
 c18:	80 95       	com	r24
 c1a:	70 95       	com	r23
 c1c:	61 95       	neg	r22
 c1e:	7f 4f       	sbci	r23, 0xFF	; 255
 c20:	8f 4f       	sbci	r24, 0xFF	; 255
 c22:	9f 4f       	sbci	r25, 0xFF	; 255
 c24:	08 95       	ret

00000c26 <__umulhisi3>:
 c26:	a2 9f       	mul	r26, r18
 c28:	b0 01       	movw	r22, r0
 c2a:	b3 9f       	mul	r27, r19
 c2c:	c0 01       	movw	r24, r0
 c2e:	a3 9f       	mul	r26, r19
 c30:	70 0d       	add	r23, r0
 c32:	81 1d       	adc	r24, r1
 c34:	11 24       	eor	r1, r1
 c36:	91 1d       	adc	r25, r1
 c38:	b2 9f       	mul	r27, r18
 c3a:	70 0d       	add	r23, r0
 c3c:	81 1d       	adc	r24, r1
 c3e:	11 24       	eor	r1, r1
 c40:	91 1d       	adc	r25, r1
 c42:	08 95       	ret

00000c44 <__udivmodsi4>:
 c44:	a1 e2       	ldi	r26, 0x21	; 33
 c46:	1a 2e       	mov	r1, r26
 c48:	aa 1b       	sub	r26, r26
 c4a:	bb 1b       	sub	r27, r27
 c4c:	fd 01       	movw	r30, r26
 c4e:	0d c0       	rjmp	.+26     	; 0xc6a <__udivmodsi4_ep>

00000c50 <__udivmodsi4_loop>:
 c50:	aa 1f       	adc	r26, r26
 c52:	bb 1f       	adc	r27, r27
 c54:	ee 1f       	adc	r30, r30
 c56:	ff 1f       	adc	r31, r31
 c58:	a2 17       	cp	r26, r18
 c5a:	b3 07       	cpc	r27, r19
 c5c:	e4 07       	cpc	r30, r20
 c5e:	f5 07       	cpc	r31, r21
 c60:	20 f0       	brcs	.+8      	; 0xc6a <__udivmodsi4_ep>
 c62:	a2 1b       	sub	r26, r18
 c64:	b3 0b       	sbc	r27, r19
 c66:	e4 0b       	sbc	r30, r20
 c68:	f5 0b       	sbc	r31, r21

00000c6a <__udivmodsi4_ep>:
 c6a:	66 1f       	adc	r22, r22
 c6c:	77 1f       	adc	r23, r23
 c6e:	88 1f       	adc	r24, r24
 c70:	99 1f       	adc	r25, r25
 c72:	1a 94       	dec	r1
 c74:	69 f7       	brne	.-38     	; 0xc50 <__udivmodsi4_loop>
 c76:	60 95       	com	r22
 c78:	70 95       	com	r23
 c7a:	80 95       	com	r24
 c7c:	90 95       	com	r25
 c7e:	9b 01       	movw	r18, r22
 c80:	ac 01       	movw	r20, r24
 c82:	bd 01       	movw	r22, r26
 c84:	cf 01       	movw	r24, r30
 c86:	08 95       	ret

00000c88 <_exit>:
 c88:	f8 94       	cli

00000c8a <__stop_program>:
 c8a:	ff cf       	rjmp	.-2      	; 0xc8a <__stop_program>