HA_Sensor_Raumklima.elf:     file format elf32-avr


Disassembly of section .text:

00000000 <__vectors>:
   0:	0c 94 34 00 	jmp	0x68	; 0x68 <__ctors_end>
   4:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
   8:	0c 94 44 02 	jmp	0x488	; 0x488 <__vector_2>
   c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  10:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  14:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  18:	0c 94 5e 00 	jmp	0xbc	; 0xbc <__vector_6>
  1c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  20:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  24:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  28:	0c 94 68 00 	jmp	0xd0	; 0xd0 <__vector_10>
  2c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  30:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  34:	0c 94 87 00 	jmp	0x10e	; 0x10e <__vector_13>
  38:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  3c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  40:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  44:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  48:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  4c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  50:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  54:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  58:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  5c:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  60:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>
  64:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__bad_interrupt>

00000068 <__ctors_end>:
  68:	11 24       	eor	r1, r1
  6a:	1f be       	out	0x3f, r1	; 63
  6c:	cf ef       	ldi	r28, 0xFF	; 255
  6e:	d4 e0       	ldi	r29, 0x04	; 4
  70:	de bf       	out	0x3e, r29	; 62
  72:	cd bf       	out	0x3d, r28	; 61

00000074 <__do_copy_data>:
  74:	11 e0       	ldi	r17, 0x01	; 1
  76:	a0 e0       	ldi	r26, 0x00	; 0
  78:	b1 e0       	ldi	r27, 0x01	; 1
  7a:	e6 ee       	ldi	r30, 0xE6	; 230
  7c:	fb e0       	ldi	r31, 0x0B	; 11
  7e:	02 c0       	rjmp	.+4      	; 0x84 <__do_copy_data+0x10>
  80:	05 90       	lpm	r0, Z+
  82:	0d 92       	st	X+, r0
  84:	a2 30       	cpi	r26, 0x02	; 2
  86:	b1 07       	cpc	r27, r17
  88:	d9 f7       	brne	.-10     	; 0x80 <__do_copy_data+0xc>

0000008a <__do_clear_bss>:
  8a:	21 e0       	ldi	r18, 0x01	; 1
  8c:	a2 e0       	ldi	r26, 0x02	; 2
  8e:	b1 e0       	ldi	r27, 0x01	; 1
  90:	01 c0       	rjmp	.+2      	; 0x94 <.do_clear_bss_start>

00000092 <.do_clear_bss_loop>:
  92:	1d 92       	st	X+, r1

00000094 <.do_clear_bss_start>:
  94:	ae 32       	cpi	r26, 0x2E	; 46
  96:	b2 07       	cpc	r27, r18
  98:	e1 f7       	brne	.-8      	; 0x92 <.do_clear_bss_loop>
  9a:	0e 94 ab 05 	call	0xb56	; 0xb56 <main>
  9e:	0c 94 f1 05 	jmp	0xbe2	; 0xbe2 <_exit>

000000a2 <__bad_interrupt>:
  a2:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>

000000a6 <setupWatchdogInterrupt>:


// set Watchdog Timer to periodically generate an interrupt
void setupWatchdogInterrupt( void)
{
	cli();															// ensure the magic below cannot be interrupted
  a6:	f8 94       	cli
	wdt_reset();
  a8:	a8 95       	wdr
	WDTCSR |= (1<<WDCE) | (1<<WDE);									// magic: start the special timed sequence required to change the watchdog control register
  aa:	e0 e6       	ldi	r30, 0x60	; 96
  ac:	f0 e0       	ldi	r31, 0x00	; 0
  ae:	80 81       	ld	r24, Z
  b0:	88 61       	ori	r24, 0x18	; 24
  b2:	80 83       	st	Z, r24
	WDTCSR  =   (1<<WDIE)											// set watchdog:	Watchdog Interrupt Enable
  b4:	86 e4       	ldi	r24, 0x46	; 70
  b6:	80 83       	st	Z, r24
			  | WDT_PRESCALER;										//					Prescaler Value
	sei();
  b8:	78 94       	sei
  ba:	08 95       	ret

000000bc <__vector_6>:
}


ISR( WDT_vect)
{
  bc:	1f 92       	push	r1
  be:	0f 92       	push	r0
  c0:	0f b6       	in	r0, 0x3f	; 63
  c2:	0f 92       	push	r0
  c4:	11 24       	eor	r1, r1
	// note: a watchdog timer reset is automatically done per hardware the ISR is executed, hence wdt_reset() is superfluous here
}
  c6:	0f 90       	pop	r0
  c8:	0f be       	out	0x3f, r0	; 63
  ca:	0f 90       	pop	r0
  cc:	1f 90       	pop	r1
  ce:	18 95       	reti

000000d0 <__vector_10>:
/******************************************************************************
* Interrupt Service Routines
******************************************************************************/

ISR( TIMER1_CAPT_vect )
{
  d0:	1f 92       	push	r1
  d2:	0f 92       	push	r0
  d4:	0f b6       	in	r0, 0x3f	; 63
  d6:	0f 92       	push	r0
  d8:	11 24       	eor	r1, r1
  da:	8f 93       	push	r24
  dc:	9f 93       	push	r25
	TCCR1B ^= (1<<ICES1);					// toggle the Input Capture Edge Selection (because there is no "match any edge" mode)
  de:	80 91 81 00 	lds	r24, 0x0081
  e2:	90 e4       	ldi	r25, 0x40	; 64
  e4:	89 27       	eor	r24, r25
  e6:	80 93 81 00 	sts	0x0081, r24

	if ( signalEdgeNeedsProcessing )		// damn, we are too late: the last edge has not been processed yet in the data-acquisition-loop
  ea:	80 91 0a 01 	lds	r24, 0x010A
  ee:	88 23       	and	r24, r24
  f0:	21 f0       	breq	.+8      	; 0xfa <__vector_10+0x2a>
		signalEdgeMissed = true;
  f2:	81 e0       	ldi	r24, 0x01	; 1
  f4:	80 93 03 01 	sts	0x0103, r24
  f8:	03 c0       	rjmp	.+6      	; 0x100 <__vector_10+0x30>
	else
		signalEdgeNeedsProcessing = true;	// flag the detection of the edge to the processing loop
  fa:	81 e0       	ldi	r24, 0x01	; 1
  fc:	80 93 0a 01 	sts	0x010A, r24
}
 100:	9f 91       	pop	r25
 102:	8f 91       	pop	r24
 104:	0f 90       	pop	r0
 106:	0f be       	out	0x3f, r0	; 63
 108:	0f 90       	pop	r0
 10a:	1f 90       	pop	r1
 10c:	18 95       	reti

0000010e <__vector_13>:


// only reached in case of an error in the data reading/data processing (e.g. when the sensor fails or is not present at all)
ISR( TIMER1_OVF_vect )
{
 10e:	1f 92       	push	r1
 110:	0f 92       	push	r0
 112:	0f b6       	in	r0, 0x3f	; 63
 114:	0f 92       	push	r0
 116:	11 24       	eor	r1, r1
 118:	8f 93       	push	r24
	signalEdgeMissed = true;				// just a trick to force the data processing loop to exit
 11a:	81 e0       	ldi	r24, 0x01	; 1
 11c:	80 93 03 01 	sts	0x0103, r24
}
 120:	8f 91       	pop	r24
 122:	0f 90       	pop	r0
 124:	0f be       	out	0x3f, r0	; 63
 126:	0f 90       	pop	r0
 128:	1f 90       	pop	r1
 12a:	18 95       	reti

0000012c <startInputCaptureTimer>:
******************************************************************************/

void startInputCaptureTimer()
{
	// mode 0: Clear Timer on Compare (CTC) mode with TOP=0xFFFF
	TCCR1A	= (0<<WGM11) | (0<<WGM10);					// mode 0
 12c:	10 92 80 00 	sts	0x0080, r1
	TCCR1B	= (0<<WGM13) | (0<<WGM12);
 130:	e1 e8       	ldi	r30, 0x81	; 129
 132:	f0 e0       	ldi	r31, 0x00	; 0
 134:	10 82       	st	Z, r1
	TCCR1B |= (1<<ICNC1);								// activate noise control for input capture
 136:	80 81       	ld	r24, Z
 138:	80 68       	ori	r24, 0x80	; 128
 13a:	80 83       	st	Z, r24
	TCCR1B |= (0<<ICES1);								// falling edge mode (note: the first edge to be detected is a falling one, the ISR ought to toggle that bit for each detected edge)
 13c:	80 81       	ld	r24, Z
 13e:	80 83       	st	Z, r24
	// enables the Input Capture Interrupt
	// (as well as the Timer Overflow Interrupt in order be able to detect a missing sensor signal, which otherwise would block execution)
	TCCR1B |= PRESCALER_BITMASK;						// starts the timer/counter running
 140:	80 81       	ld	r24, Z
 142:	82 60       	ori	r24, 0x02	; 2
 144:	80 83       	st	Z, r24
	TIMSK1 |= (1<<ICIE1) | (1<<TOIE1);
 146:	ef e6       	ldi	r30, 0x6F	; 111
 148:	f0 e0       	ldi	r31, 0x00	; 0
 14a:	80 81       	ld	r24, Z
 14c:	81 62       	ori	r24, 0x21	; 33
 14e:	80 83       	st	Z, r24
	cli();	// §§§ muss spätestens vor dem letzten Befehl stehen, dieser ist allerdings beliebig (setting TCCR1B, TIMSK1, TCNT1)
 150:	f8 94       	cli
	TCNT1	= 0;										// reset counter value
 152:	10 92 85 00 	sts	0x0085, r1
 156:	10 92 84 00 	sts	0x0084, r1
	ICR1	= 0;										// reset input capture register (neccessary!)
 15a:	10 92 87 00 	sts	0x0087, r1
 15e:	10 92 86 00 	sts	0x0086, r1
 162:	08 95       	ret

00000164 <stopInputCaptureTimer>:
}


void stopInputCaptureTimer( void)
{
	TIMSK1 = 0;											// disable all Timer1 related interrupts
 164:	10 92 6f 00 	sts	0x006F, r1
	TCCR1B &= ~( (1<<CS12) | (1<<CS11) | (1<<CS10) );	// stop timer/counter
 168:	e1 e8       	ldi	r30, 0x81	; 129
 16a:	f0 e0       	ldi	r31, 0x00	; 0
 16c:	80 81       	ld	r24, Z
 16e:	88 7f       	andi	r24, 0xF8	; 248
 170:	80 83       	st	Z, r24
 172:	08 95       	ret

00000174 <acquire_DHT>:
}


// acquires data transfer from the DHT-sensor
bool acquire_DHT()
{
 174:	ef 92       	push	r14
 176:	ff 92       	push	r15
 178:	0f 93       	push	r16
 17a:	1f 93       	push	r17
 17c:	cf 93       	push	r28
 17e:	df 93       	push	r29
 180:	00 d0       	rcall	.+0      	; 0x182 <acquire_DHT+0xe>
 182:	cd b7       	in	r28, 0x3d	; 61
 184:	de b7       	in	r29, 0x3e	; 62
	uint8_t		iEdge = 0;							// counts signal level changes
	uint16_t	last_time = 0;						// time of previous signal edge (in microseconds)
	uint16_t	current_time = 0;					// time of current	signal edge (in microseconds)
	uint16_t	duration = 0;						// time between the last two signal edges
	
	volatile uint16_t	var_divisor = ( F_CPU / PRESCALER_VALUE / 1000 );
 186:	80 ed       	ldi	r24, 0xD0	; 208
 188:	97 e0       	ldi	r25, 0x07	; 7
 18a:	9a 83       	std	Y+2, r25	; 0x02
 18c:	89 83       	std	Y+1, r24	; 0x01

	// ensure High level for some time
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );
 18e:	28 9a       	sbi	0x05, 0	; 5
	SENSOR_DDR	|=	(1<<SENSOR_DD_BIT);
 190:	20 9a       	sbi	0x04, 0	; 4
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 192:	8f e9       	ldi	r24, 0x9F	; 159
 194:	9f e0       	ldi	r25, 0x0F	; 15
 196:	01 97       	sbiw	r24, 0x01	; 1
 198:	f1 f7       	brne	.-4      	; 0x196 <acquire_DHT+0x22>
 19a:	00 c0       	rjmp	.+0      	; 0x19c <acquire_DHT+0x28>
 19c:	00 00       	nop
	_delay_ms( 1);									// § how long do we have to wait at least?

	// send start condition (18ms low)
	SENSOR_PORT &= ~(1<<SENSOR_PIN	 );
 19e:	28 98       	cbi	0x05, 0	; 5
 1a0:	9f ef       	ldi	r25, 0xFF	; 255
 1a2:	20 ee       	ldi	r18, 0xE0	; 224
 1a4:	60 e0       	ldi	r22, 0x00	; 0
 1a6:	91 50       	subi	r25, 0x01	; 1
 1a8:	20 40       	sbci	r18, 0x00	; 0
 1aa:	60 40       	sbci	r22, 0x00	; 0
 1ac:	e1 f7       	brne	.-8      	; 0x1a6 <acquire_DHT+0x32>
 1ae:	00 c0       	rjmp	.+0      	; 0x1b0 <acquire_DHT+0x3c>
 1b0:	00 00       	nop
	_delay_ms( 18);									// note: in case of the DHT22, 800us would be enough (which can be used to distinguish both models)

	// prepare and start listening
	data0=0; data1=0; data2=0; data3=0; data4=0;
 1b2:	10 92 07 01 	sts	0x0107, r1
 1b6:	10 92 04 01 	sts	0x0104, r1
 1ba:	10 92 05 01 	sts	0x0105, r1
 1be:	10 92 09 01 	sts	0x0109, r1
 1c2:	10 92 06 01 	sts	0x0106, r1
	dataIsValid = false;
 1c6:	10 92 08 01 	sts	0x0108, r1
	iEdge = 0;
	signalEdgeNeedsProcessing = false;
 1ca:	10 92 0a 01 	sts	0x010A, r1
	signalEdgeMissed = false;
 1ce:	10 92 03 01 	sts	0x0103, r1
	cli();											// §§ why exactely is this needed?
 1d2:	f8 94       	cli
	startInputCaptureTimer();
 1d4:	0e 94 96 00 	call	0x12c	; 0x12c <startInputCaptureTimer>
	sei();
 1d8:	78 94       	sei

	// (actively driven = fast) raising edge, then set IO as input with pull-up activ
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );
 1da:	28 9a       	sbi	0x05, 0	; 5
	SENSOR_DDR	&= ~(1<<SENSOR_DD_BIT);
 1dc:	20 98       	cbi	0x04, 0	; 4

// acquires data transfer from the DHT-sensor
bool acquire_DHT()
{
	uint8_t		iEdge = 0;							// counts signal level changes
	uint16_t	last_time = 0;						// time of previous signal edge (in microseconds)
 1de:	20 e0       	ldi	r18, 0x00	; 0
 1e0:	30 e0       	ldi	r19, 0x00	; 0
	_delay_ms( 18);									// note: in case of the DHT22, 800us would be enough (which can be used to distinguish both models)

	// prepare and start listening
	data0=0; data1=0; data2=0; data3=0; data4=0;
	dataIsValid = false;
	iEdge = 0;
 1e2:	f1 2c       	mov	r15, r1
						{ stopDataTransfer(); break; }		// error
				}
				else										// odd number -> falling edge after 26-28us (representing logic 0) or 70us (representing logic 1)
				{
					uint8_t iByte = (iEdge-5) / 2 / 8;		// 5: first data edge, 2: edges per bit, 8: bits per byte
					uint8_t iBit  = 7 - ( (iEdge-5) / 2 % 8 );		// LSB first
 1e4:	07 e0       	ldi	r16, 0x07	; 7
 1e6:	e0 2e       	mov	r14, r16
						switch ( iByte ) { case 0: data0 &= ~(1<<iBit); break; case 1: data1 &= ~(1<<iBit); break; case 2: data2 &= ~(1<<iBit); break; case 3: data3 &= ~(1<<iBit); break; case 4: data4 &= ~(1<<iBit); break; }
					}
					else if (  duration > 75-TOLERANCE && duration < 75+TOLERANCE )
					{
						// data[iByte] |=	(1<<iBit);			// bit = 1
						switch ( iByte ) { case 0: data0 |= (1<<iBit); break; case 1: data1 |= (1<<iBit); break; case 2: data2 |= (1<<iBit); break; case 3: data3 |= (1<<iBit); break; case 4: data4 |= (1<<iBit); break; }
 1e8:	41 e0       	ldi	r20, 0x01	; 1
 1ea:	50 e0       	ldi	r21, 0x00	; 0
	// (actively driven = fast) raising edge, then set IO as input with pull-up activ
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );
	SENSOR_DDR	&= ~(1<<SENSOR_DD_BIT);
	
	// process data provided from IRQ-driven sensor reading
	while ( ! signalEdgeMissed	)					// note: besides this the loop may be left by "break;"
 1ec:	80 91 03 01 	lds	r24, 0x0103
 1f0:	81 11       	cpse	r24, r1
 1f2:	e8 c0       	rjmp	.+464    	; 0x3c4 <acquire_DHT+0x250>
	{
		if ( signalEdgeNeedsProcessing )			// set by ISR each time a signal level change is detected and its time stored in ICR1
 1f4:	80 91 0a 01 	lds	r24, 0x010A
 1f8:	88 23       	and	r24, r24
 1fa:	c1 f3       	breq	.-16     	; 0x1ec <acquire_DHT+0x78>
		{
			iEdge++;
 1fc:	f3 94       	inc	r15
			// AVOID 64bit integer arithmetic like "current_time = ICR1 * 1000000ULL / ( F_CPU / PRESCALER_VALUE );"
			// §§§ The following assignment induces VERY STRANGE ERRORNEOUS BEHAVIOUR:
			// current_time = 1000L * ICR1 / ( F_CPU / PRESCALER_VALUE / 1000 );	// §§§ error
			// §§	 The only solution I have found is to put the term ( F_CPU / PRESCALER_VALUE / 1000 ) into a constant.
			//	   Not into a variable, this will fail too ;)
			current_time = 1000L * ICR1 / CONST_DIVISOR;							// okay
 1fe:	80 91 86 00 	lds	r24, 0x0086
 202:	90 91 87 00 	lds	r25, 0x0087
 206:	a0 e0       	ldi	r26, 0x00	; 0
 208:	b0 e0       	ldi	r27, 0x00	; 0
 20a:	b5 95       	asr	r27
 20c:	a7 95       	ror	r26
 20e:	97 95       	ror	r25
 210:	87 95       	ror	r24
			duration	 = current_time - last_time;
			last_time	 = current_time;
			
			// at this point, the Input Capture may be triggered again without loss of data, so tell this to be okay now
			asm volatile ("" : : : "memory");				// "compiler barrier" which ensures the compiler does not move the code around
			signalEdgeNeedsProcessing = false;
 212:	10 92 0a 01 	sts	0x010A, r1

			if ( iEdge == 1 )								// begin of start response: 80us low, then 80us high
 216:	61 e0       	ldi	r22, 0x01	; 1
 218:	f6 16       	cp	r15, r22
 21a:	09 f4       	brne	.+2      	; 0x21e <acquire_DHT+0xaa>
 21c:	d1 c0       	rjmp	.+418    	; 0x3c0 <acquire_DHT+0x24c>
			// current_time = 1000L * ICR1 / ( F_CPU / PRESCALER_VALUE / 1000 );	// §§§ error
			// §§	 The only solution I have found is to put the term ( F_CPU / PRESCALER_VALUE / 1000 ) into a constant.
			//	   Not into a variable, this will fail too ;)
			current_time = 1000L * ICR1 / CONST_DIVISOR;							// okay
			// current_time = 1000L * ICR1 / var_divisor;       // §§§ error	<-------------------- BÖSER FEHLER -------------------->
			duration	 = current_time - last_time;
 21e:	bc 01       	movw	r22, r24
 220:	62 1b       	sub	r22, r18
 222:	73 0b       	sbc	r23, r19
			asm volatile ("" : : : "memory");				// "compiler barrier" which ensures the compiler does not move the code around
			signalEdgeNeedsProcessing = false;

			if ( iEdge == 1 )								// begin of start response: 80us low, then 80us high
			{}												// the current time is recorded as last_time, nothing else is to be done here
			else if ( iEdge <= 3 )							// end of 80us low (iEdge==2) or end of 80us high (iEdge==3)
 224:	23 e0       	ldi	r18, 0x03	; 3
 226:	2f 15       	cp	r18, r15
 228:	38 f0       	brcs	.+14     	; 0x238 <acquire_DHT+0xc4>
			{
				if (  duration < 80-TOLERANCE || duration > 80+TOLERANCE )
 22a:	61 54       	subi	r22, 0x41	; 65
 22c:	71 09       	sbc	r23, r1
 22e:	6f 31       	cpi	r22, 0x1F	; 31
 230:	71 05       	cpc	r23, r1
 232:	08 f4       	brcc	.+2      	; 0x236 <acquire_DHT+0xc2>
 234:	c5 c0       	rjmp	.+394    	; 0x3c0 <acquire_DHT+0x24c>
 236:	c1 c0       	rjmp	.+386    	; 0x3ba <acquire_DHT+0x246>
					{ stopDataTransfer(); break; }			// error
			}
			else											// sensor transmits 40 data bits (LSB first)
			{
				if ( ! ( iEdge % 2 ) )						// even number -> rising edge after 50us
 238:	f0 fc       	sbrc	r15, 0
 23a:	03 c0       	rjmp	.+6      	; 0x242 <acquire_DHT+0xce>
				{
					if (  duration < 55-TOLERANCE || duration > 55+TOLERANCE )
 23c:	68 52       	subi	r22, 0x28	; 40
 23e:	71 09       	sbc	r23, r1
 240:	f6 cf       	rjmp	.-20     	; 0x22e <acquire_DHT+0xba>
						{ stopDataTransfer(); break; }		// error
				}
				else										// odd number -> falling edge after 26-28us (representing logic 0) or 70us (representing logic 1)
				{
					uint8_t iByte = (iEdge-5) / 2 / 8;		// 5: first data edge, 2: edges per bit, 8: bits per byte
 242:	0f 2d       	mov	r16, r15
 244:	10 e0       	ldi	r17, 0x00	; 0
 246:	f8 01       	movw	r30, r16
 248:	35 97       	sbiw	r30, 0x05	; 5
 24a:	9f 01       	movw	r18, r30
 24c:	f7 ff       	sbrs	r31, 7
 24e:	02 c0       	rjmp	.+4      	; 0x254 <acquire_DHT+0xe0>
 250:	21 5f       	subi	r18, 0xF1	; 241
 252:	3f 4f       	sbci	r19, 0xFF	; 255
 254:	b4 e0       	ldi	r27, 0x04	; 4
 256:	35 95       	asr	r19
 258:	27 95       	ror	r18
 25a:	ba 95       	dec	r27
 25c:	e1 f7       	brne	.-8      	; 0x256 <acquire_DHT+0xe2>
					uint8_t iBit  = 7 - ( (iEdge-5) / 2 % 8 );		// LSB first
 25e:	f7 fd       	sbrc	r31, 7
 260:	31 96       	adiw	r30, 0x01	; 1
 262:	f5 95       	asr	r31
 264:	e7 95       	ror	r30
 266:	e7 70       	andi	r30, 0x07	; 7
 268:	ff 27       	eor	r31, r31
 26a:	1e 2d       	mov	r17, r14
 26c:	1e 1b       	sub	r17, r30
					if (  duration > 26-TOLERANCE/2 && duration < 28+TOLERANCE/2 )
 26e:	fb 01       	movw	r30, r22
 270:	74 97       	sbiw	r30, 0x14	; 20
 272:	3f 97       	sbiw	r30, 0x0f	; 15
 274:	08 f0       	brcs	.+2      	; 0x278 <acquire_DHT+0x104>
 276:	48 c0       	rjmp	.+144    	; 0x308 <acquire_DHT+0x194>
					{
						// data[iByte] &= ~(1<<iBit);			// bit = 0
						switch ( iByte ) { case 0: data0 &= ~(1<<iBit); break; case 1: data1 &= ~(1<<iBit); break; case 2: data2 &= ~(1<<iBit); break; case 3: data3 &= ~(1<<iBit); break; case 4: data4 &= ~(1<<iBit); break; }
 278:	22 30       	cpi	r18, 0x02	; 2
 27a:	31 05       	cpc	r19, r1
 27c:	79 f1       	breq	.+94     	; 0x2dc <acquire_DHT+0x168>
 27e:	8c f4       	brge	.+34     	; 0x2a2 <acquire_DHT+0x12e>
 280:	21 15       	cp	r18, r1
 282:	31 05       	cpc	r19, r1
 284:	01 f1       	breq	.+64     	; 0x2c6 <acquire_DHT+0x152>
 286:	21 30       	cpi	r18, 0x01	; 1
 288:	31 05       	cpc	r19, r1
 28a:	09 f0       	breq	.+2      	; 0x28e <acquire_DHT+0x11a>
 28c:	90 c0       	rjmp	.+288    	; 0x3ae <acquire_DHT+0x23a>
 28e:	01 2e       	mov	r0, r17
 290:	01 c0       	rjmp	.+2      	; 0x294 <acquire_DHT+0x120>
 292:	22 0f       	add	r18, r18
 294:	0a 94       	dec	r0
 296:	ea f7       	brpl	.-6      	; 0x292 <acquire_DHT+0x11e>
 298:	20 95       	com	r18
 29a:	30 91 04 01 	lds	r19, 0x0104
 29e:	32 23       	and	r19, r18
 2a0:	69 c0       	rjmp	.+210    	; 0x374 <acquire_DHT+0x200>
 2a2:	23 30       	cpi	r18, 0x03	; 3
 2a4:	31 05       	cpc	r19, r1
 2a6:	29 f1       	breq	.+74     	; 0x2f2 <acquire_DHT+0x17e>
 2a8:	24 30       	cpi	r18, 0x04	; 4
 2aa:	31 05       	cpc	r19, r1
 2ac:	09 f0       	breq	.+2      	; 0x2b0 <acquire_DHT+0x13c>
 2ae:	7f c0       	rjmp	.+254    	; 0x3ae <acquire_DHT+0x23a>
 2b0:	9a 01       	movw	r18, r20
 2b2:	01 2e       	mov	r0, r17
 2b4:	01 c0       	rjmp	.+2      	; 0x2b8 <acquire_DHT+0x144>
 2b6:	22 0f       	add	r18, r18
 2b8:	0a 94       	dec	r0
 2ba:	ea f7       	brpl	.-6      	; 0x2b6 <acquire_DHT+0x142>
 2bc:	20 95       	com	r18
 2be:	30 91 06 01 	lds	r19, 0x0106
 2c2:	32 23       	and	r19, r18
 2c4:	72 c0       	rjmp	.+228    	; 0x3aa <acquire_DHT+0x236>
 2c6:	9a 01       	movw	r18, r20
 2c8:	01 2e       	mov	r0, r17
 2ca:	01 c0       	rjmp	.+2      	; 0x2ce <acquire_DHT+0x15a>
 2cc:	22 0f       	add	r18, r18
 2ce:	0a 94       	dec	r0
 2d0:	ea f7       	brpl	.-6      	; 0x2cc <acquire_DHT+0x158>
 2d2:	20 95       	com	r18
 2d4:	30 91 07 01 	lds	r19, 0x0107
 2d8:	32 23       	and	r19, r18
 2da:	49 c0       	rjmp	.+146    	; 0x36e <acquire_DHT+0x1fa>
 2dc:	9a 01       	movw	r18, r20
 2de:	01 2e       	mov	r0, r17
 2e0:	01 c0       	rjmp	.+2      	; 0x2e4 <acquire_DHT+0x170>
 2e2:	22 0f       	add	r18, r18
 2e4:	0a 94       	dec	r0
 2e6:	ea f7       	brpl	.-6      	; 0x2e2 <acquire_DHT+0x16e>
 2e8:	20 95       	com	r18
 2ea:	30 91 05 01 	lds	r19, 0x0105
 2ee:	32 23       	and	r19, r18
 2f0:	4d c0       	rjmp	.+154    	; 0x38c <acquire_DHT+0x218>
 2f2:	9a 01       	movw	r18, r20
 2f4:	01 2e       	mov	r0, r17
 2f6:	01 c0       	rjmp	.+2      	; 0x2fa <acquire_DHT+0x186>
 2f8:	22 0f       	add	r18, r18
 2fa:	0a 94       	dec	r0
 2fc:	ea f7       	brpl	.-6      	; 0x2f8 <acquire_DHT+0x184>
 2fe:	20 95       	com	r18
 300:	30 91 09 01 	lds	r19, 0x0109
 304:	32 23       	and	r19, r18
 306:	4e c0       	rjmp	.+156    	; 0x3a4 <acquire_DHT+0x230>
					}
					else if (  duration > 75-TOLERANCE && duration < 75+TOLERANCE )
 308:	6d 53       	subi	r22, 0x3D	; 61
 30a:	71 09       	sbc	r23, r1
 30c:	6d 31       	cpi	r22, 0x1D	; 29
 30e:	71 05       	cpc	r23, r1
 310:	08 f0       	brcs	.+2      	; 0x314 <acquire_DHT+0x1a0>
 312:	53 c0       	rjmp	.+166    	; 0x3ba <acquire_DHT+0x246>
					{
						// data[iByte] |=	(1<<iBit);			// bit = 1
						switch ( iByte ) { case 0: data0 |= (1<<iBit); break; case 1: data1 |= (1<<iBit); break; case 2: data2 |= (1<<iBit); break; case 3: data3 |= (1<<iBit); break; case 4: data4 |= (1<<iBit); break; }
 314:	22 30       	cpi	r18, 0x02	; 2
 316:	31 05       	cpc	r19, r1
 318:	81 f1       	breq	.+96     	; 0x37a <acquire_DHT+0x206>
 31a:	84 f4       	brge	.+32     	; 0x33c <acquire_DHT+0x1c8>
 31c:	21 15       	cp	r18, r1
 31e:	31 05       	cpc	r19, r1
 320:	e9 f0       	breq	.+58     	; 0x35c <acquire_DHT+0x1e8>
 322:	21 30       	cpi	r18, 0x01	; 1
 324:	31 05       	cpc	r19, r1
 326:	09 f0       	breq	.+2      	; 0x32a <acquire_DHT+0x1b6>
 328:	42 c0       	rjmp	.+132    	; 0x3ae <acquire_DHT+0x23a>
 32a:	01 2e       	mov	r0, r17
 32c:	01 c0       	rjmp	.+2      	; 0x330 <acquire_DHT+0x1bc>
 32e:	22 0f       	add	r18, r18
 330:	0a 94       	dec	r0
 332:	ea f7       	brpl	.-6      	; 0x32e <acquire_DHT+0x1ba>
 334:	30 91 04 01 	lds	r19, 0x0104
 338:	32 2b       	or	r19, r18
 33a:	1c c0       	rjmp	.+56     	; 0x374 <acquire_DHT+0x200>
 33c:	23 30       	cpi	r18, 0x03	; 3
 33e:	31 05       	cpc	r19, r1
 340:	41 f1       	breq	.+80     	; 0x392 <acquire_DHT+0x21e>
 342:	24 30       	cpi	r18, 0x04	; 4
 344:	31 05       	cpc	r19, r1
 346:	99 f5       	brne	.+102    	; 0x3ae <acquire_DHT+0x23a>
 348:	9a 01       	movw	r18, r20
 34a:	01 2e       	mov	r0, r17
 34c:	01 c0       	rjmp	.+2      	; 0x350 <acquire_DHT+0x1dc>
 34e:	22 0f       	add	r18, r18
 350:	0a 94       	dec	r0
 352:	ea f7       	brpl	.-6      	; 0x34e <acquire_DHT+0x1da>
 354:	30 91 06 01 	lds	r19, 0x0106
 358:	32 2b       	or	r19, r18
 35a:	27 c0       	rjmp	.+78     	; 0x3aa <acquire_DHT+0x236>
 35c:	9a 01       	movw	r18, r20
 35e:	01 2e       	mov	r0, r17
 360:	01 c0       	rjmp	.+2      	; 0x364 <acquire_DHT+0x1f0>
 362:	22 0f       	add	r18, r18
 364:	0a 94       	dec	r0
 366:	ea f7       	brpl	.-6      	; 0x362 <acquire_DHT+0x1ee>
 368:	30 91 07 01 	lds	r19, 0x0107
 36c:	32 2b       	or	r19, r18
 36e:	30 93 07 01 	sts	0x0107, r19
 372:	1d c0       	rjmp	.+58     	; 0x3ae <acquire_DHT+0x23a>
 374:	30 93 04 01 	sts	0x0104, r19
 378:	1a c0       	rjmp	.+52     	; 0x3ae <acquire_DHT+0x23a>
 37a:	9a 01       	movw	r18, r20
 37c:	01 2e       	mov	r0, r17
 37e:	01 c0       	rjmp	.+2      	; 0x382 <acquire_DHT+0x20e>
 380:	22 0f       	add	r18, r18
 382:	0a 94       	dec	r0
 384:	ea f7       	brpl	.-6      	; 0x380 <acquire_DHT+0x20c>
 386:	30 91 05 01 	lds	r19, 0x0105
 38a:	32 2b       	or	r19, r18
 38c:	30 93 05 01 	sts	0x0105, r19
 390:	0e c0       	rjmp	.+28     	; 0x3ae <acquire_DHT+0x23a>
 392:	9a 01       	movw	r18, r20
 394:	01 2e       	mov	r0, r17
 396:	01 c0       	rjmp	.+2      	; 0x39a <acquire_DHT+0x226>
 398:	22 0f       	add	r18, r18
 39a:	0a 94       	dec	r0
 39c:	ea f7       	brpl	.-6      	; 0x398 <acquire_DHT+0x224>
 39e:	30 91 09 01 	lds	r19, 0x0109
 3a2:	32 2b       	or	r19, r18
 3a4:	30 93 09 01 	sts	0x0109, r19
 3a8:	02 c0       	rjmp	.+4      	; 0x3ae <acquire_DHT+0x23a>
 3aa:	30 93 06 01 	sts	0x0106, r19
					}
					else
						{ stopDataTransfer(); break; }		// error
					if ( iEdge == 83 )						// final bit edge
 3ae:	63 e5       	ldi	r22, 0x53	; 83
 3b0:	f6 12       	cpse	r15, r22
 3b2:	06 c0       	rjmp	.+12     	; 0x3c0 <acquire_DHT+0x24c>
					{
						dataIsValid = true;					// SUCCESS
 3b4:	81 e0       	ldi	r24, 0x01	; 1
 3b6:	80 93 08 01 	sts	0x0108, r24
						stopDataTransfer(); break;
 3ba:	0e 94 b2 00 	call	0x164	; 0x164 <stopInputCaptureTimer>
 3be:	02 c0       	rjmp	.+4      	; 0x3c4 <acquire_DHT+0x250>
}


// acquires data transfer from the DHT-sensor
bool acquire_DHT()
{
 3c0:	9c 01       	movw	r18, r24
 3c2:	14 cf       	rjmp	.-472    	; 0x1ec <acquire_DHT+0x78>
			}	// if ( iEdge <= 3 ) ... else
		}	// if ( signalEdgeNeedsProcessing )
	}	// while ( ! signalEdgeMissed ) - or left by "break;"

	// stop timer/counter1 and reset port pin
	stopInputCaptureTimer();
 3c4:	0e 94 b2 00 	call	0x164	; 0x164 <stopInputCaptureTimer>
	SENSOR_PORT |=	(1<<SENSOR_PIN	 );				// high
 3c8:	28 9a       	sbi	0x05, 0	; 5
	SENSOR_DDR	|=	(1<<SENSOR_DD_BIT);				// out
 3ca:	20 9a       	sbi	0x04, 0	; 4

	// check checksum
	uint8_t sum = (uint8_t)(data0 + data1 + data2 + data3);
 3cc:	80 91 04 01 	lds	r24, 0x0104
 3d0:	90 91 07 01 	lds	r25, 0x0107
 3d4:	89 0f       	add	r24, r25
 3d6:	90 91 05 01 	lds	r25, 0x0105
 3da:	89 0f       	add	r24, r25
 3dc:	90 91 09 01 	lds	r25, 0x0109
 3e0:	89 0f       	add	r24, r25
	if ( sum != data4 )
 3e2:	90 91 06 01 	lds	r25, 0x0106
 3e6:	89 13       	cpse	r24, r25
		dataIsValid = false;
 3e8:	10 92 08 01 	sts	0x0108, r1

	return	dataIsValid;
}	// bool acquire_DHT()
 3ec:	80 91 08 01 	lds	r24, 0x0108
 3f0:	0f 90       	pop	r0
 3f2:	0f 90       	pop	r0
 3f4:	df 91       	pop	r29
 3f6:	cf 91       	pop	r28
 3f8:	1f 91       	pop	r17
 3fa:	0f 91       	pop	r16
 3fc:	ff 90       	pop	r15
 3fe:	ef 90       	pop	r14
 400:	08 95       	ret

00000402 <get_humidity>:

#if DHT_TYPE == DHT_TYPE_DHT11

	uint8_t get_humidity( void)
	{
		if ( dataIsValid )
 402:	80 91 08 01 	lds	r24, 0x0108
 406:	88 23       	and	r24, r24
 408:	19 f0       	breq	.+6      	; 0x410 <get_humidity+0xe>
			return data0;
 40a:	80 91 07 01 	lds	r24, 0x0107
 40e:	08 95       	ret
		else
			return 0;
 410:	80 e0       	ldi	r24, 0x00	; 0
	}
 412:	08 95       	ret

00000414 <get_temperature>:

	int8_t get_temperature( void)
	{
		if ( dataIsValid )
 414:	80 91 08 01 	lds	r24, 0x0108
 418:	88 23       	and	r24, r24
 41a:	19 f0       	breq	.+6      	; 0x422 <get_temperature+0xe>
			return data2;
 41c:	80 91 05 01 	lds	r24, 0x0105
 420:	08 95       	ret
		else
			return 0;	// § may be better to use an impossible value too
 422:	80 e0       	ldi	r24, 0x00	; 0
	}
 424:	08 95       	ret

00000426 <spi_init>:

// Initialize pins and registers for spi communication
void spi_init()
{
	// define port pins as input
    DDR_SPI &= ~( (1<<DD_MISO) );
 426:	24 98       	cbi	0x04, 4	; 4
	// define port pins as output
    DDR_SPI |=  ( (1<<DD_MOSI) | (1<<DD_SS) | (1<<DD_SCK) );
 428:	84 b1       	in	r24, 0x04	; 4
 42a:	8c 62       	ori	r24, 0x2C	; 44
 42c:	84 b9       	out	0x04, r24	; 4
    
    SPCR = (   (1<<SPE)				// SPI Enable
 42e:	81 e5       	ldi	r24, 0x51	; 81
 430:	8c bd       	out	0x2c, r24	; 44
             | (0<<SPR1)
			 | (1<<SPR0)			// SPI Clock Rate
             | (0<<CPOL)			// Clock Polarity (0:SCK low / 1:SCK hi when idle)		§ may need to be adapted
             | (0<<CPHA)			// Clock Phase (0:leading / 1:trailing edge sampling)	§ may need to be adapted
		   );
    SPSR = (1<<SPI2X);				// Double Clock Rate = 8 MHz (§ use with care, since not all SPI devices support this)
 432:	81 e0       	ldi	r24, 0x01	; 1
 434:	8d bd       	out	0x2d, r24	; 45
 436:	08 95       	ret

00000438 <spi_stop>:


// Deactivates the SPI module (use in order to save current when going to sleep/power down)
void spi_stop()
{
    SPCR &= ~(1<<SPE);				// SPI Enable
 438:	8c b5       	in	r24, 0x2c	; 44
 43a:	8f 7b       	andi	r24, 0xBF	; 191
 43c:	8c bd       	out	0x2c, r24	; 44
 43e:	08 95       	ret

00000440 <spi_transfer_byte>:


// Writes one byte to target device and returns the received one
uint8_t spi_transfer_byte( uint8_t data)
{
    SPDR = data;
 440:	8e bd       	out	0x2e, r24	; 46
    while ( !( SPSR & (1<<SPIF) ) );
 442:	0d b4       	in	r0, 0x2d	; 45
 444:	07 fe       	sbrs	r0, 7
 446:	fd cf       	rjmp	.-6      	; 0x442 <spi_transfer_byte+0x2>
    return SPDR;
 448:	8e b5       	in	r24, 0x2e	; 46
}
 44a:	08 95       	ret

0000044c <spi_transfer>:


// Writes an byte-array of len bytes to target device and returns the bytes received
void spi_transfer( uint8_t * dataout, uint8_t * datain, uint8_t len)
{
 44c:	26 2f       	mov	r18, r22
	for ( uint8_t i = 0; i < len; i++ )
 44e:	fb 01       	movw	r30, r22
 450:	3e 2f       	mov	r19, r30
 452:	32 1b       	sub	r19, r18
 454:	34 17       	cp	r19, r20
 456:	50 f4       	brcc	.+20     	; 0x46c <spi_transfer+0x20>
	{
		SPDR = dataout[i];
 458:	dc 01       	movw	r26, r24
 45a:	3d 91       	ld	r19, X+
 45c:	cd 01       	movw	r24, r26
 45e:	3e bd       	out	0x2e, r19	; 46
		while ( !( SPSR & (1<<SPIF) ) );
 460:	0d b4       	in	r0, 0x2d	; 45
 462:	07 fe       	sbrs	r0, 7
 464:	fd cf       	rjmp	.-6      	; 0x460 <spi_transfer+0x14>
		datain[i] = SPDR;
 466:	3e b5       	in	r19, 0x2e	; 46
 468:	31 93       	st	Z+, r19
 46a:	f2 cf       	rjmp	.-28     	; 0x450 <spi_transfer+0x4>
	}
}
 46c:	08 95       	ret

0000046e <spi_transmit>:


// Writes an byte-array of len bytes to target device and discards the bytes received
void spi_transmit( uint8_t * dataout, uint8_t len)
{
 46e:	28 2f       	mov	r18, r24
	for ( uint8_t i = 0; i < len; i++)
 470:	fc 01       	movw	r30, r24
 472:	8e 2f       	mov	r24, r30
 474:	82 1b       	sub	r24, r18
 476:	86 17       	cp	r24, r22
 478:	30 f4       	brcc	.+12     	; 0x486 <spi_transmit+0x18>
	{
		SPDR = dataout[i];
 47a:	81 91       	ld	r24, Z+
 47c:	8e bd       	out	0x2e, r24	; 46
		while ( !( SPSR & (1<<SPIF) ) );
 47e:	0d b4       	in	r0, 0x2d	; 45
 480:	07 fe       	sbrs	r0, 7
 482:	fd cf       	rjmp	.-6      	; 0x47e <spi_transmit+0x10>
 484:	f6 cf       	rjmp	.-20     	; 0x472 <spi_transmit+0x4>
	}
}
 486:	08 95       	ret

00000488 <__vector_2>:
#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega88A__) || defined(__AVR_ATmega168__)
ISR( INT1_vect )
#else
#	error MCU MODEL NOT SUPPORTED
#endif // defined(__AVR_ATmega8__) || defined(__AVR_ATmega88A__) || defined(__AVR_ATmega168__)
{
 488:	1f 92       	push	r1
 48a:	0f 92       	push	r0
 48c:	0f b6       	in	r0, 0x3f	; 63
 48e:	0f 92       	push	r0
 490:	11 24       	eor	r1, r1
 492:	8f 93       	push	r24
	// just flag the IRQ (processing of status/data as well as resetting of the flag variable has to be done in the main loop)
	lib_nRF24L01_IRQ_scheduled = true;
 494:	81 e0       	ldi	r24, 0x01	; 1
 496:	80 93 2d 01 	sts	0x012D, r24
}
 49a:	8f 91       	pop	r24
 49c:	0f 90       	pop	r0
 49e:	0f be       	out	0x3f, r0	; 63
 4a0:	0f 90       	pop	r0
 4a2:	1f 90       	pop	r1
 4a4:	18 95       	reti

000004a6 <lib_nRF24L01_reuse_TX_FIFO>:


// schedules the current TX FIFO to be sent again (after a packet is lost)
void lib_nRF24L01_reuse_TX_FIFO( void)
{
	lib_nRF24L01_EXECUTE(
 4a6:	5d 98       	cbi	0x0b, 5	; 11
 4a8:	83 ee       	ldi	r24, 0xE3	; 227
 4aa:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 4ae:	5d 9a       	sbi	0x0b, 5	; 11
 4b0:	08 95       	ret

000004b2 <lib_nRF24L01_flush_TX_FIFO>:
}


void lib_nRF24L01_flush_TX_FIFO( void)
{
	lib_nRF24L01_EXECUTE(
 4b2:	5d 98       	cbi	0x0b, 5	; 11
 4b4:	81 ee       	ldi	r24, 0xE1	; 225
 4b6:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 4ba:	5d 9a       	sbi	0x0b, 5	; 11
 4bc:	08 95       	ret

000004be <lib_nRF24L01_flush_RX_FIFO>:
}


void lib_nRF24L01_flush_RX_FIFO( void)
{
	lib_nRF24L01_EXECUTE(
 4be:	5d 98       	cbi	0x0b, 5	; 11
 4c0:	81 ee       	ldi	r24, 0xE1	; 225
 4c2:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 4c6:	5d 9a       	sbi	0x0b, 5	; 11
 4c8:	08 95       	ret

000004ca <lib_nRF24L01_set_CE_high>:
//-----------------------------------------------------------------------------

// Chip Enable Control: start RX/TX operation
void lib_nRF24L01_set_CE_high()
{
	lib_nRF24L01_CONTROL_PORT |=  _BV(lib_nRF24L01_CE_PIN );
 4ca:	5c 9a       	sbi	0x0b, 4	; 11
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 4cc:	85 e1       	ldi	r24, 0x15	; 21
 4ce:	8a 95       	dec	r24
 4d0:	f1 f7       	brne	.-4      	; 0x4ce <lib_nRF24L01_set_CE_high+0x4>
 4d2:	00 00       	nop
	_delay_us( nRF24L01_DELAY_CE_HIGH_2_CSN_LOW);
	currentState |=  STATE_BITMASK_ACTIVE;
 4d4:	80 91 02 01 	lds	r24, 0x0102
 4d8:	88 60       	ori	r24, 0x08	; 8
 4da:	80 93 02 01 	sts	0x0102, r24
 4de:	08 95       	ret

000004e0 <lib_nRF24L01_set_CE_low>:


// Chip Enable Control: stop RX/TX operation
void lib_nRF24L01_set_CE_low()
{
	lib_nRF24L01_CONTROL_PORT &= ~_BV(lib_nRF24L01_CE_PIN );
 4e0:	5c 98       	cbi	0x0b, 4	; 11
	currentState &= ~STATE_BITMASK_ACTIVE;
 4e2:	80 91 02 01 	lds	r24, 0x0102
 4e6:	87 7f       	andi	r24, 0xF7	; 247
 4e8:	80 93 02 01 	sts	0x0102, r24
 4ec:	08 95       	ret

000004ee <lib_nRF24L01_init_MCU>:

// Initializes MCU-pins to communicate with the lib_nRF24L01.
void lib_nRF24L01_init_MCU()
{
	// Initialize SPI in mode 0 (CPOL=0 und CPHA=0)
	spi_init();						// §§ uses the libs default SPI mode without checking whether this is appropriate
 4ee:	0e 94 13 02 	call	0x426	; 0x426 <spi_init>

	// Define CSN- and CE-pins as output and set them to default values
	lib_nRF24L01_CONTROL_DDR |= _BV(lib_nRF24L01_CSN_PIN) | _BV(lib_nRF24L01_CE_PIN);	// § note: this coding abuses the identity of port value register bit position as well as data direction register bit position
 4f2:	8a b1       	in	r24, 0x0a	; 10
 4f4:	80 63       	ori	r24, 0x30	; 48
 4f6:	8a b9       	out	0x0a, r24	; 10
	lib_nRF24L01_SET_CSN_HIGH;		// SPI Chip Select = false
 4f8:	5d 9a       	sbi	0x0b, 5	; 11
	lib_nRF24L01_set_CE_low();		// nRF24L01 Chip Enable = false (i.e. the nRF24L01 stays in passive mode)
 4fa:	0e 94 70 02 	call	0x4e0	; 0x4e0 <lib_nRF24L01_set_CE_low>
	MCUCR |=  _BV(ISC11);			// Interrupt Sense Control Bits: generate external interrupt INT0 on falling edge
	MCUCR &= ~_BV(ISC10);
	GICR  |=  _BV(INT1);			// Activate INT0
#elif defined(__AVR_ATmega88A__) || defined(__AVR_ATmega168__) || defined(__AVR_ATmega328__)
	// ... external interrupt 1 (PD3)
	EICRA |=  _BV(ISC11);			// External Interrupt Control Bits: generate interrupt on falling edge for INT0
 4fe:	e9 e6       	ldi	r30, 0x69	; 105
 500:	f0 e0       	ldi	r31, 0x00	; 0
 502:	80 81       	ld	r24, Z
 504:	88 60       	ori	r24, 0x08	; 8
 506:	80 83       	st	Z, r24
	EICRA &= ~_BV(ISC10);
 508:	80 81       	ld	r24, Z
 50a:	8b 7f       	andi	r24, 0xFB	; 251
 50c:	80 83       	st	Z, r24
	EIMSK |=  _BV(INT1);			// Activate INT0
 50e:	e9 9a       	sbi	0x1d, 1	; 29
 510:	08 95       	ret

00000512 <lib_nRF24L01_TriggerSingleTrans>:

// Start single transmission by a high pulse on CE pin. Note: 10uS is the minimal allowable pulse length.
// If the CE signal is already high, this function returns without doing anything.
void lib_nRF24L01_TriggerSingleTrans()
{
	if ( ! (currentState & STATE_BITMASK_ACTIVE) )
 512:	80 91 02 01 	lds	r24, 0x0102
 516:	83 fd       	sbrc	r24, 3
 518:	08 c0       	rjmp	.+16     	; 0x52a <lib_nRF24L01_TriggerSingleTrans+0x18>
	{
		lib_nRF24L01_set_CE_high();
 51a:	0e 94 65 02 	call	0x4ca	; 0x4ca <lib_nRF24L01_set_CE_high>
 51e:	8a e6       	ldi	r24, 0x6A	; 106
 520:	8a 95       	dec	r24
 522:	f1 f7       	brne	.-4      	; 0x520 <lib_nRF24L01_TriggerSingleTrans+0xe>
 524:	00 c0       	rjmp	.+0      	; 0x526 <lib_nRF24L01_TriggerSingleTrans+0x14>
		_delay_us( 2 * nRF24L01_DELAY_MIN_CE_HIGH);		// § Caution: there are versions of nRF24L01 modules, which have been reported not to work with a delay of 10us.
		lib_nRF24L01_set_CE_low();
 526:	0c 94 70 02 	jmp	0x4e0	; 0x4e0 <lib_nRF24L01_set_CE_low>
 52a:	08 95       	ret

0000052c <lib_nRF24L01_start>:

// Puts the nRF24L01 into operation (i.e. receiving or transmitting messages depending on the current configuration).
// If the nRF24L01 is currently active, the operation is stopped and then restarted in order to make sure it operates according to the current mode configuration.
void lib_nRF24L01_start()
{
	if (   (currentState & STATE_BITMASK_ACTIVE) )
 52c:	80 91 02 01 	lds	r24, 0x0102
 530:	83 ff       	sbrs	r24, 3
 532:	06 c0       	rjmp	.+12     	; 0x540 <lib_nRF24L01_start+0x14>
	{
		lib_nRF24L01_set_CE_low();						// stop active operation (switch into standby mode)
 534:	0e 94 70 02 	call	0x4e0	; 0x4e0 <lib_nRF24L01_set_CE_low>
 538:	85 e3       	ldi	r24, 0x35	; 53
 53a:	8a 95       	dec	r24
 53c:	f1 f7       	brne	.-4      	; 0x53a <lib_nRF24L01_start+0xe>
 53e:	00 00       	nop
		_delay_us( nRF24L01_DELAY_CE_LOW_2_CE_HIGH);
	}
	lib_nRF24L01_set_CE_high();							// start active operation
 540:	0e 94 65 02 	call	0x4ca	; 0x4ca <lib_nRF24L01_set_CE_high>

	// The nRF24L01+ needs 130us to sync its PLL and start operation after CE goes high.
	// In RX mode we do not have to bother about that, since polling/IRQ-driven message receiving will always work as expected.
	// But in TX mode we may ought to ensure the TX FIFO cannot be written to before the nRF24L01+ is ready. 	§§ check if really neccessary
	if ( ! (currentState & STATE_BITMASK_RX_MODE) )
 544:	80 91 02 01 	lds	r24, 0x0102
 548:	82 fd       	sbrc	r24, 2
 54a:	06 c0       	rjmp	.+12     	; 0x558 <lib_nRF24L01_start+0x2c>
 54c:	87 e0       	ldi	r24, 0x07	; 7
 54e:	92 e0       	ldi	r25, 0x02	; 2
 550:	01 97       	sbiw	r24, 0x01	; 1
 552:	f1 f7       	brne	.-4      	; 0x550 <lib_nRF24L01_start+0x24>
 554:	00 c0       	rjmp	.+0      	; 0x556 <lib_nRF24L01_start+0x2a>
 556:	00 00       	nop
 558:	08 95       	ret

0000055a <lib_nRF24L01_stop>:


// Puts the nRF24L01+ into standby-mode (i.e. leaves TX/RX active modes)
void lib_nRF24L01_stop()
{
	lib_nRF24L01_set_CE_low();
 55a:	0c 94 70 02 	jmp	0x4e0	; 0x4e0 <lib_nRF24L01_set_CE_low>

0000055e <lib_nRF24L01_get_regbyte>:
// low level functions (read/write nRF24L01+ registers)
//-----------------------------------------------------------------------------

// Reads one byte from the given nRF24L01-module register
uint8_t lib_nRF24L01_get_regbyte( uint8_t reg)
{
 55e:	cf 93       	push	r28
 560:	df 93       	push	r29
 562:	1f 92       	push	r1
 564:	cd b7       	in	r28, 0x3d	; 61
 566:	de b7       	in	r29, 0x3e	; 62
	uint8_t byteval;
	lib_nRF24L01_EXECUTE(
 568:	5d 98       	cbi	0x0b, 5	; 11
 56a:	8f 71       	andi	r24, 0x1F	; 31
 56c:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 570:	41 e0       	ldi	r20, 0x01	; 1
 572:	be 01       	movw	r22, r28
 574:	6f 5f       	subi	r22, 0xFF	; 255
 576:	7f 4f       	sbci	r23, 0xFF	; 255
 578:	cb 01       	movw	r24, r22
 57a:	0e 94 26 02 	call	0x44c	; 0x44c <spi_transfer>
 57e:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_R_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_transfer_sync( &byteval, &byteval, 1);
	)
	return byteval;
}
 580:	89 81       	ldd	r24, Y+1	; 0x01
 582:	0f 90       	pop	r0
 584:	df 91       	pop	r29
 586:	cf 91       	pop	r28
 588:	08 95       	ret

0000058a <lib_nRF24L01_set_regbyte>:


// Writes one byte into the given nRF24L01-module register
void lib_nRF24L01_set_regbyte( uint8_t reg, uint8_t value)
{
 58a:	cf 93       	push	r28
 58c:	df 93       	push	r29
 58e:	1f 92       	push	r1
 590:	cd b7       	in	r28, 0x3d	; 61
 592:	de b7       	in	r29, 0x3e	; 62
	lib_nRF24L01_EXECUTE(
 594:	5d 98       	cbi	0x0b, 5	; 11
 596:	8f 71       	andi	r24, 0x1F	; 31
 598:	80 62       	ori	r24, 0x20	; 32
 59a:	69 83       	std	Y+1, r22	; 0x01
 59c:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 5a0:	69 81       	ldd	r22, Y+1	; 0x01
 5a2:	86 2f       	mov	r24, r22
 5a4:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 5a8:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_W_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_fast_shift( value);
	)
}
 5aa:	0f 90       	pop	r0
 5ac:	df 91       	pop	r29
 5ae:	cf 91       	pop	r28
 5b0:	08 95       	ret

000005b2 <lib_nRF24L01_invoke_RX_mode>:

// Sets nRF24L01-registers for RX mode and powers it up into standby mode.
// If the nRF24L01 is currently set active, this state will NOT be left. In this case you need to stop/restart active operation in order to activate the RX mode.
void lib_nRF24L01_invoke_RX_mode()
{
	lib_nRF24L01_set_regbyte( nRF_REG_CONFIG,   lib_nRF24L01_CONFIG
 5b2:	6f e0       	ldi	r22, 0x0F	; 15
 5b4:	80 e0       	ldi	r24, 0x00	; 0
 5b6:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
											  | nRF_REGBITMASK_CONFIG_PWR_UP
											  | nRF_REGBITMASK_CONFIG_PRIM_RX
							);

	if ( ! (currentState & STATE_BITMASK_PWR_UP) )
 5ba:	80 91 02 01 	lds	r24, 0x0102
 5be:	81 fd       	sbrc	r24, 1
 5c0:	06 c0       	rjmp	.+12     	; 0x5ce <lib_nRF24L01_invoke_RX_mode+0x1c>
 5c2:	8f e6       	ldi	r24, 0x6F	; 111
 5c4:	97 e1       	ldi	r25, 0x17	; 23
 5c6:	01 97       	sbiw	r24, 0x01	; 1
 5c8:	f1 f7       	brne	.-4      	; 0x5c6 <lib_nRF24L01_invoke_RX_mode+0x14>
 5ca:	00 c0       	rjmp	.+0      	; 0x5cc <lib_nRF24L01_invoke_RX_mode+0x1a>
 5cc:	00 00       	nop
		_delay_us( nRF24L01_DELAY_POWERUP);

	currentState |= ( STATE_BITMASK_PWR_UP | STATE_BITMASK_RX_MODE );
 5ce:	80 91 02 01 	lds	r24, 0x0102
 5d2:	86 60       	ori	r24, 0x06	; 6
 5d4:	80 93 02 01 	sts	0x0102, r24
 5d8:	08 95       	ret

000005da <lib_nRF24L01_invoke_TX_mode>:
// The PTX-device address will be set to the address assigned to this RX data pipe.
// Note: when using "auto acknowledgement", RX_Address_Pipe_0 must be the same as the TX-address, since it is used to receive the ack payload from the receiver.
// If the nRF24L01 is currently set active, this state will NOT be left. In this case you need to stop/restart active operation in order to activate the TX mode.
void lib_nRF24L01_invoke_TX_mode( void)
{
	lib_nRF24L01_set_regbyte( nRF_REG_CONFIG,   lib_nRF24L01_CONFIG
 5da:	6e e0       	ldi	r22, 0x0E	; 14
 5dc:	80 e0       	ldi	r24, 0x00	; 0
 5de:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
											  | nRF_REGBITMASK_CONFIG_PWR_UP
							);

	if ( ! (currentState & STATE_BITMASK_PWR_UP) )
 5e2:	80 91 02 01 	lds	r24, 0x0102
 5e6:	81 fd       	sbrc	r24, 1
 5e8:	06 c0       	rjmp	.+12     	; 0x5f6 <lib_nRF24L01_invoke_TX_mode+0x1c>
 5ea:	8f e6       	ldi	r24, 0x6F	; 111
 5ec:	97 e1       	ldi	r25, 0x17	; 23
 5ee:	01 97       	sbiw	r24, 0x01	; 1
 5f0:	f1 f7       	brne	.-4      	; 0x5ee <lib_nRF24L01_invoke_TX_mode+0x14>
 5f2:	00 c0       	rjmp	.+0      	; 0x5f4 <lib_nRF24L01_invoke_TX_mode+0x1a>
 5f4:	00 00       	nop
		_delay_us( nRF24L01_DELAY_POWERUP);

	currentState |=  STATE_BITMASK_PWR_UP;
	currentState &= ~STATE_BITMASK_RX_MODE;
 5f6:	80 91 02 01 	lds	r24, 0x0102
 5fa:	8b 7f       	andi	r24, 0xFB	; 251
 5fc:	82 60       	ori	r24, 0x02	; 2
 5fe:	80 93 02 01 	sts	0x0102, r24
 602:	08 95       	ret

00000604 <lib_nRF24L01_get_data>:


// Read at most maxBytes bytes from received packet data into array payload.
// Note that the nRF24L01+ deletes the whole FIFO slot afterwards.
void lib_nRF24L01_get_data( uint8_t * payload, uint8_t maxBytes)
{
 604:	ff 92       	push	r15
 606:	0f 93       	push	r16
 608:	1f 93       	push	r17
 60a:	cf 93       	push	r28
 60c:	df 93       	push	r29
 60e:	1f 92       	push	r1
 610:	cd b7       	in	r28, 0x3d	; 61
 612:	de b7       	in	r29, 0x3e	; 62
 614:	8c 01       	movw	r16, r24
 616:	f6 2e       	mov	r15, r22
	uint8_t payloadWidth;

#ifdef DEBUG2
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 100);
#endif
	lib_nRF24L01_EXECUTE(
 618:	5d 98       	cbi	0x0b, 5	; 11
 61a:	80 e6       	ldi	r24, 0x60	; 96
 61c:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 620:	61 e0       	ldi	r22, 0x01	; 1
 622:	ce 01       	movw	r24, r28
 624:	01 96       	adiw	r24, 0x01	; 1
 626:	0e 94 37 02 	call	0x46e	; 0x46e <spi_transmit>
 62a:	5d 9a       	sbi	0x0b, 5	; 11
		spi_transmit_sync( &payloadWidth, 1);											// Get payload width	§§ korrekt?
	)
#ifdef DEBUG2
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 100);
#endif
	lib_nRF24L01_EXECUTE(
 62c:	5d 98       	cbi	0x0b, 5	; 11
 62e:	81 e6       	ldi	r24, 0x61	; 97
 630:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 634:	89 81       	ldd	r24, Y+1	; 0x01
 636:	4f 2d       	mov	r20, r15
 638:	f8 16       	cp	r15, r24
 63a:	08 f4       	brcc	.+2      	; 0x63e <lib_nRF24L01_get_data+0x3a>
 63c:	48 2f       	mov	r20, r24
 63e:	b8 01       	movw	r22, r16
 640:	c8 01       	movw	r24, r16
 642:	0e 94 26 02 	call	0x44c	; 0x44c <spi_transfer>
 646:	5d 9a       	sbi	0x0b, 5	; 11
		spi_transfer_sync( payload, payload, max( payloadWidth, maxBytes) );			// Read payload
	)
#ifdef DEBUG2
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 100);
#endif
	lib_nRF24L01_set_regbyte( nRF_REG_STATUS, nRF_REGBITMASK_STATUS_RX_DR);				// Reset RX_DR flag
 648:	60 e4       	ldi	r22, 0x40	; 64
 64a:	87 e0       	ldi	r24, 0x07	; 7
 64c:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
}
 650:	0f 90       	pop	r0
 652:	df 91       	pop	r29
 654:	cf 91       	pop	r28
 656:	1f 91       	pop	r17
 658:	0f 91       	pop	r16
 65a:	ff 90       	pop	r15
 65c:	08 95       	ret

0000065e <lib_nRF24L01_read_register>:


// Reads an array of bytes from the given start position in the nRF24L01-module registers.
// Returns value of nRF24L01 status register before any changes are done.
void lib_nRF24L01_read_register( uint8_t reg, uint8_t * value, uint8_t len)
{
 65e:	0f 93       	push	r16
 660:	1f 93       	push	r17
 662:	cf 93       	push	r28
 664:	df 93       	push	r29
 666:	1f 92       	push	r1
 668:	cd b7       	in	r28, 0x3d	; 61
 66a:	de b7       	in	r29, 0x3e	; 62
 66c:	8b 01       	movw	r16, r22
	lib_nRF24L01_EXECUTE(
 66e:	5d 98       	cbi	0x0b, 5	; 11
 670:	8f 71       	andi	r24, 0x1F	; 31
 672:	49 83       	std	Y+1, r20	; 0x01
 674:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 678:	49 81       	ldd	r20, Y+1	; 0x01
 67a:	b8 01       	movw	r22, r16
 67c:	c8 01       	movw	r24, r16
 67e:	0e 94 26 02 	call	0x44c	; 0x44c <spi_transfer>
 682:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_R_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_transfer_sync( value, value, len);
	)
}
 684:	0f 90       	pop	r0
 686:	df 91       	pop	r29
 688:	cf 91       	pop	r28
 68a:	1f 91       	pop	r17
 68c:	0f 91       	pop	r16
 68e:	08 95       	ret

00000690 <lib_nRF24L01_TX_FIFO_is_full>:
// FIFO control
//-----------------------------------------------------------------------------

// returns true if there is a free TX FIFO available
bool lib_nRF24L01_TX_FIFO_is_full()
{
 690:	cf 93       	push	r28
 692:	df 93       	push	r29
 694:	1f 92       	push	r1
 696:	cd b7       	in	r28, 0x3d	; 61
 698:	de b7       	in	r29, 0x3e	; 62
	uint8_t fifo_status;
	lib_nRF24L01_read_register( nRF_REG_FIFO_STATUS, &fifo_status, 1);
 69a:	41 e0       	ldi	r20, 0x01	; 1
 69c:	be 01       	movw	r22, r28
 69e:	6f 5f       	subi	r22, 0xFF	; 255
 6a0:	7f 4f       	sbci	r23, 0xFF	; 255
 6a2:	87 e1       	ldi	r24, 0x17	; 23
 6a4:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	return ( fifo_status & nRF_REGBITMASK_FIFO_STATUS_TX_FULL );
 6a8:	89 81       	ldd	r24, Y+1	; 0x01
}
 6aa:	85 fb       	bst	r24, 5
 6ac:	88 27       	eor	r24, r24
 6ae:	80 f9       	bld	r24, 0
 6b0:	0f 90       	pop	r0
 6b2:	df 91       	pop	r29
 6b4:	cf 91       	pop	r28
 6b6:	08 95       	ret

000006b8 <lib_nRF24L01_write_TX_FIFO>:
// Writes packet data into TX FIFO.
// Returns false, if this fails because there is no free TX FIFO available, otherwise returns true.
// Note: - if the nRF24L01+ is in TX mode and CE is high, the data will be sent immediately.
//       - if the nRF24L01+ is in TX mode and CE is low , lib_nRF24L01_TriggerSingleTrans() (or lib_nRF24L01_start()) must be called to send the data
bool lib_nRF24L01_write_TX_FIFO( uint8_t * data, uint8_t len)
{
 6b8:	0f 93       	push	r16
 6ba:	1f 93       	push	r17
 6bc:	cf 93       	push	r28
 6be:	df 93       	push	r29
 6c0:	1f 92       	push	r1
 6c2:	cd b7       	in	r28, 0x3d	; 61
 6c4:	de b7       	in	r29, 0x3e	; 62
 6c6:	8c 01       	movw	r16, r24
	if ( lib_nRF24L01_TX_FIFO_is_full() )			// check for free FIFO
 6c8:	69 83       	std	Y+1, r22	; 0x01
 6ca:	0e 94 48 03 	call	0x690	; 0x690 <lib_nRF24L01_TX_FIFO_is_full>
 6ce:	69 81       	ldd	r22, Y+1	; 0x01
 6d0:	81 11       	cpse	r24, r1
 6d2:	0c c0       	rjmp	.+24     	; 0x6ec <lib_nRF24L01_write_TX_FIFO+0x34>
		return false;
	else
	{
		lib_nRF24L01_EXECUTE(
 6d4:	5d 98       	cbi	0x0b, 5	; 11
 6d6:	80 ea       	ldi	r24, 0xA0	; 160
 6d8:	69 83       	std	Y+1, r22	; 0x01
 6da:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 6de:	69 81       	ldd	r22, Y+1	; 0x01
 6e0:	c8 01       	movw	r24, r16
 6e2:	0e 94 37 02 	call	0x46e	; 0x46e <spi_transmit>
 6e6:	5d 9a       	sbi	0x0b, 5	; 11
 6e8:	81 e0       	ldi	r24, 0x01	; 1
 6ea:	01 c0       	rjmp	.+2      	; 0x6ee <lib_nRF24L01_write_TX_FIFO+0x36>
// Note: - if the nRF24L01+ is in TX mode and CE is high, the data will be sent immediately.
//       - if the nRF24L01+ is in TX mode and CE is low , lib_nRF24L01_TriggerSingleTrans() (or lib_nRF24L01_start()) must be called to send the data
bool lib_nRF24L01_write_TX_FIFO( uint8_t * data, uint8_t len)
{
	if ( lib_nRF24L01_TX_FIFO_is_full() )			// check for free FIFO
		return false;
 6ec:	80 e0       	ldi	r24, 0x00	; 0
			spi_fast_shift( nRF_CMD_W_TX_PAYLOAD );
			spi_transmit_sync( data, len);
		)
		return true;
	}
}
 6ee:	0f 90       	pop	r0
 6f0:	df 91       	pop	r29
 6f2:	cf 91       	pop	r28
 6f4:	1f 91       	pop	r17
 6f6:	0f 91       	pop	r16
 6f8:	08 95       	ret

000006fa <lib_nRF24L01_TX_FIFO_is_empty>:
}


// returns true if TX_EMPTY bit in FIFO_STATUS register is set, false otherwise
bool lib_nRF24L01_TX_FIFO_is_empty()
{
 6fa:	cf 93       	push	r28
 6fc:	df 93       	push	r29
 6fe:	1f 92       	push	r1
 700:	cd b7       	in	r28, 0x3d	; 61
 702:	de b7       	in	r29, 0x3e	; 62
	uint8_t fifo_status;
	lib_nRF24L01_read_register( nRF_REG_FIFO_STATUS, &fifo_status, 1);
 704:	41 e0       	ldi	r20, 0x01	; 1
 706:	be 01       	movw	r22, r28
 708:	6f 5f       	subi	r22, 0xFF	; 255
 70a:	7f 4f       	sbci	r23, 0xFF	; 255
 70c:	87 e1       	ldi	r24, 0x17	; 23
 70e:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	return ( fifo_status & nRF_REGBITMASK_FIFO_STATUS_TX_EMPTY );
 712:	89 81       	ldd	r24, Y+1	; 0x01
}
 714:	82 95       	swap	r24
 716:	81 70       	andi	r24, 0x01	; 1
 718:	0f 90       	pop	r0
 71a:	df 91       	pop	r29
 71c:	cf 91       	pop	r28
 71e:	08 95       	ret

00000720 <lib_nRF24L01_send>:
// sending/transmitting data
//-----------------------------------------------------------------------------

// Simple implementation of sending a single data package
void lib_nRF24L01_send( uint8_t * data, uint8_t len)
{
 720:	1f 93       	push	r17
 722:	cf 93       	push	r28
 724:	df 93       	push	r29
 726:	ec 01       	movw	r28, r24
 728:	16 2f       	mov	r17, r22
	if ( currentState & STATE_BITMASK_ACTIVE )			// in this case a packet written into an TX FIFO will be sent as soon as possible
 72a:	80 91 02 01 	lds	r24, 0x0102
 72e:	83 ff       	sbrs	r24, 3
 730:	07 c0       	rjmp	.+14     	; 0x740 <lib_nRF24L01_send+0x20>
	{
		while ( ! lib_nRF24L01_write_TX_FIFO( data, len) ) {}
 732:	61 2f       	mov	r22, r17
 734:	ce 01       	movw	r24, r28
 736:	0e 94 5c 03 	call	0x6b8	; 0x6b8 <lib_nRF24L01_write_TX_FIFO>
 73a:	88 23       	and	r24, r24
 73c:	d1 f3       	breq	.-12     	; 0x732 <lib_nRF24L01_send+0x12>
 73e:	10 c0       	rjmp	.+32     	; 0x760 <lib_nRF24L01_send+0x40>
	}
	else	// each packet has to be triggered separately
	{
		while ( ! lib_nRF24L01_TX_FIFO_is_empty() )		// first transmit all non empty FIFO slots
 740:	0e 94 7d 03 	call	0x6fa	; 0x6fa <lib_nRF24L01_TX_FIFO_is_empty>
 744:	81 11       	cpse	r24, r1
 746:	03 c0       	rjmp	.+6      	; 0x74e <lib_nRF24L01_send+0x2e>
		{
			lib_nRF24L01_TriggerSingleTrans();
 748:	0e 94 89 02 	call	0x512	; 0x512 <lib_nRF24L01_TriggerSingleTrans>
 74c:	f9 cf       	rjmp	.-14     	; 0x740 <lib_nRF24L01_send+0x20>
		}
		lib_nRF24L01_write_TX_FIFO( data, len);
 74e:	61 2f       	mov	r22, r17
 750:	ce 01       	movw	r24, r28
 752:	0e 94 5c 03 	call	0x6b8	; 0x6b8 <lib_nRF24L01_write_TX_FIFO>
		lib_nRF24L01_TriggerSingleTrans();
	}
}
 756:	df 91       	pop	r29
 758:	cf 91       	pop	r28
 75a:	1f 91       	pop	r17
		while ( ! lib_nRF24L01_TX_FIFO_is_empty() )		// first transmit all non empty FIFO slots
		{
			lib_nRF24L01_TriggerSingleTrans();
		}
		lib_nRF24L01_write_TX_FIFO( data, len);
		lib_nRF24L01_TriggerSingleTrans();
 75c:	0c 94 89 02 	jmp	0x512	; 0x512 <lib_nRF24L01_TriggerSingleTrans>
	}
}
 760:	df 91       	pop	r29
 762:	cf 91       	pop	r28
 764:	1f 91       	pop	r17
 766:	08 95       	ret

00000768 <lib_nRF24L01_RX_FIFO_is_empty>:
}


// returns true if RX_EMPTY bit in FIFO_STATUS register is set, false otherwise
bool lib_nRF24L01_RX_FIFO_is_empty()
{
 768:	cf 93       	push	r28
 76a:	df 93       	push	r29
 76c:	1f 92       	push	r1
 76e:	cd b7       	in	r28, 0x3d	; 61
 770:	de b7       	in	r29, 0x3e	; 62
	uint8_t fifo_status;
	lib_nRF24L01_read_register( nRF_REG_FIFO_STATUS, &fifo_status, 1);
 772:	41 e0       	ldi	r20, 0x01	; 1
 774:	be 01       	movw	r22, r28
 776:	6f 5f       	subi	r22, 0xFF	; 255
 778:	7f 4f       	sbci	r23, 0xFF	; 255
 77a:	87 e1       	ldi	r24, 0x17	; 23
 77c:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	return ( fifo_status & nRF_REGBITMASK_FIFO_STATUS_RX_EMPTY );
 780:	89 81       	ldd	r24, Y+1	; 0x01
}
 782:	81 70       	andi	r24, 0x01	; 1
 784:	0f 90       	pop	r0
 786:	df 91       	pop	r29
 788:	cf 91       	pop	r28
 78a:	08 95       	ret

0000078c <lib_nRF24L01_get_arc_cnt>:
}


// Returns the number of Automatic Retransmitted data packets within Current transaction (an "Enhanced Shockburst" feature)
uint8_t lib_nRF24L01_get_arc_cnt()
{
 78c:	cf 93       	push	r28
 78e:	df 93       	push	r29
 790:	1f 92       	push	r1
 792:	cd b7       	in	r28, 0x3d	; 61
 794:	de b7       	in	r29, 0x3e	; 62
	uint8_t observe_tx_data;
	lib_nRF24L01_read_register( nRF_REG_OBSERVE_TX, &observe_tx_data, 1);
 796:	41 e0       	ldi	r20, 0x01	; 1
 798:	be 01       	movw	r22, r28
 79a:	6f 5f       	subi	r22, 0xFF	; 255
 79c:	7f 4f       	sbci	r23, 0xFF	; 255
 79e:	88 e0       	ldi	r24, 0x08	; 8
 7a0:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	return ( observe_tx_data & nRF_REGBITMASK_OBSERVE_TX_ARC_CNT );
 7a4:	89 81       	ldd	r24, Y+1	; 0x01
}
 7a6:	8f 70       	andi	r24, 0x0F	; 15
 7a8:	0f 90       	pop	r0
 7aa:	df 91       	pop	r29
 7ac:	cf 91       	pop	r28
 7ae:	08 95       	ret

000007b0 <lib_nRF24L01_get_plos_cnt>:


// Returns the number of Lost data packets since the last RF channel change (an "Enhanced Shockburst" feature)
uint8_t lib_nRF24L01_get_plos_cnt()
{
 7b0:	cf 93       	push	r28
 7b2:	df 93       	push	r29
 7b4:	1f 92       	push	r1
 7b6:	cd b7       	in	r28, 0x3d	; 61
 7b8:	de b7       	in	r29, 0x3e	; 62
	uint8_t observe_tx_data;
	lib_nRF24L01_read_register( nRF_REG_OBSERVE_TX, &observe_tx_data, 1);
 7ba:	41 e0       	ldi	r20, 0x01	; 1
 7bc:	be 01       	movw	r22, r28
 7be:	6f 5f       	subi	r22, 0xFF	; 255
 7c0:	7f 4f       	sbci	r23, 0xFF	; 255
 7c2:	88 e0       	ldi	r24, 0x08	; 8
 7c4:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	return ( (observe_tx_data & nRF_REGBITMASK_OBSERVE_TX_PLOS_CNT) >> 4 );
 7c8:	89 81       	ldd	r24, Y+1	; 0x01
}
 7ca:	82 95       	swap	r24
 7cc:	8f 70       	andi	r24, 0x0F	; 15
 7ce:	0f 90       	pop	r0
 7d0:	df 91       	pop	r29
 7d2:	cf 91       	pop	r28
 7d4:	08 95       	ret

000007d6 <lib_nRF24L01_write_register>:


// Writes an array of bytes into inte the nRF24L01-module registers.
// Returns value of nRF24L01 status register before any changes are done.
void lib_nRF24L01_write_register( uint8_t reg, uint8_t * value, uint8_t len)
{
 7d6:	0f 93       	push	r16
 7d8:	1f 93       	push	r17
 7da:	cf 93       	push	r28
 7dc:	df 93       	push	r29
 7de:	1f 92       	push	r1
 7e0:	cd b7       	in	r28, 0x3d	; 61
 7e2:	de b7       	in	r29, 0x3e	; 62
 7e4:	8b 01       	movw	r16, r22
	lib_nRF24L01_EXECUTE(
 7e6:	5d 98       	cbi	0x0b, 5	; 11
 7e8:	8f 71       	andi	r24, 0x1F	; 31
 7ea:	80 62       	ori	r24, 0x20	; 32
 7ec:	49 83       	std	Y+1, r20	; 0x01
 7ee:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 7f2:	49 81       	ldd	r20, Y+1	; 0x01
 7f4:	64 2f       	mov	r22, r20
 7f6:	c8 01       	movw	r24, r16
 7f8:	0e 94 37 02 	call	0x46e	; 0x46e <spi_transmit>
 7fc:	5d 9a       	sbi	0x0b, 5	; 11
		spi_fast_shift( nRF_CMD_W_REGISTER | (nRF_CMDBITMASK_REGISTER & reg));
		spi_transmit_sync( value, len);
	)
}
 7fe:	0f 90       	pop	r0
 800:	df 91       	pop	r29
 802:	cf 91       	pop	r28
 804:	1f 91       	pop	r17
 806:	0f 91       	pop	r16
 808:	08 95       	ret

0000080a <lib_nRF24L01_power_down>:
}


// Powers the nRF24L01+ down (saves power supply current)
void lib_nRF24L01_power_down()
{
 80a:	cf 93       	push	r28
 80c:	df 93       	push	r29
 80e:	1f 92       	push	r1
 810:	cd b7       	in	r28, 0x3d	; 61
 812:	de b7       	in	r29, 0x3e	; 62
	unsigned char config;

	lib_nRF24L01_set_CE_low();		// stop active operation (recommended before powering down)
 814:	0e 94 70 02 	call	0x4e0	; 0x4e0 <lib_nRF24L01_set_CE_low>
	
	lib_nRF24L01_read_register ( nRF_REG_CONFIG, &config, 1);
 818:	41 e0       	ldi	r20, 0x01	; 1
 81a:	be 01       	movw	r22, r28
 81c:	6f 5f       	subi	r22, 0xFF	; 255
 81e:	7f 4f       	sbci	r23, 0xFF	; 255
 820:	80 e0       	ldi	r24, 0x00	; 0
 822:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	config &= ~nRF_REGBITMASK_CONFIG_PWR_UP;
 826:	89 81       	ldd	r24, Y+1	; 0x01
 828:	8d 7f       	andi	r24, 0xFD	; 253
 82a:	89 83       	std	Y+1, r24	; 0x01
	lib_nRF24L01_write_register( nRF_REG_CONFIG, &config, 1);
 82c:	41 e0       	ldi	r20, 0x01	; 1
 82e:	be 01       	movw	r22, r28
 830:	6f 5f       	subi	r22, 0xFF	; 255
 832:	7f 4f       	sbci	r23, 0xFF	; 255
 834:	80 e0       	ldi	r24, 0x00	; 0
 836:	0e 94 eb 03 	call	0x7d6	; 0x7d6 <lib_nRF24L01_write_register>
	
	currentState &= ~STATE_BITMASK_PWR_UP;
 83a:	80 91 02 01 	lds	r24, 0x0102
 83e:	8d 7f       	andi	r24, 0xFD	; 253
 840:	80 93 02 01 	sts	0x0102, r24
}
 844:	0f 90       	pop	r0
 846:	df 91       	pop	r29
 848:	cf 91       	pop	r28
 84a:	08 95       	ret

0000084c <lib_nRF24L01_set_rx_addr.part.2>:
//		If an invalid address (greater than five) is supplied, the function does nothing.
//	addr_msbs
//		pointer to all bytes except the first one of the device address to be set
//	addr_lsb
//		first byte of the device address to be set
void lib_nRF24L01_set_rx_addr( uint8_t lib_nRF24L01_pipe_num, uint8_t groupID, uint8_t deviceID)
 84c:	cf 93       	push	r28
 84e:	df 93       	push	r29
 850:	00 d0       	rcall	.+0      	; 0x852 <lib_nRF24L01_set_rx_addr.part.2+0x6>
 852:	1f 92       	push	r1
 854:	cd b7       	in	r28, 0x3d	; 61
 856:	de b7       	in	r29, 0x3e	; 62
 858:	98 2f       	mov	r25, r24
 85a:	8a e0       	ldi	r24, 0x0A	; 10
 85c:	89 0f       	add	r24, r25
{
	uint8_t address[lib_nRF24L01_ADDR_WIDTH];
	
	if ( lib_nRF24L01_pipe_num > 5 )
		return;									// §§ flag error status
	else if ( lib_nRF24L01_pipe_num < 2 )		// data pipes 0 and 1 are multi-byte address register values (byte count defined by SETUP_AW register)
 85e:	92 30       	cpi	r25, 0x02	; 2
 860:	58 f4       	brcc	.+22     	; 0x878 <lib_nRF24L01_set_rx_addr.part.2+0x2c>
	{
		address[0] = deviceID;					// LSB first
 862:	49 83       	std	Y+1, r20	; 0x01
		address[1] = groupID;
 864:	6a 83       	std	Y+2, r22	; 0x02
		address[2] = lib_nRF24L01_ADDR_MSB;
 866:	92 e4       	ldi	r25, 0x42	; 66
 868:	9b 83       	std	Y+3, r25	; 0x03
		lib_nRF24L01_write_register( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, address, lib_nRF24L01_ADDR_WIDTH);
 86a:	43 e0       	ldi	r20, 0x03	; 3
 86c:	be 01       	movw	r22, r28
 86e:	6f 5f       	subi	r22, 0xFF	; 255
 870:	7f 4f       	sbci	r23, 0xFF	; 255
 872:	0e 94 eb 03 	call	0x7d6	; 0x7d6 <lib_nRF24L01_write_register>
 876:	03 c0       	rjmp	.+6      	; 0x87e <lib_nRF24L01_set_rx_addr.part.2+0x32>
	}
	else										// data pipes 2..5 get only the deviceID assigned, because their MSBytes are the same as of data pipe 1
	{
		lib_nRF24L01_set_regbyte( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, deviceID);
 878:	64 2f       	mov	r22, r20
 87a:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
	}

	
}
 87e:	0f 90       	pop	r0
 880:	0f 90       	pop	r0
 882:	0f 90       	pop	r0
 884:	df 91       	pop	r29
 886:	cf 91       	pop	r28
 888:	08 95       	ret

0000088a <lib_nRF24L01_set_regbits>:
	)
}


void lib_nRF24L01_set_regbits( uint8_t reg, uint8_t bitmask)
{
 88a:	0f 93       	push	r16
 88c:	1f 93       	push	r17
 88e:	cf 93       	push	r28
 890:	df 93       	push	r29
 892:	1f 92       	push	r1
 894:	cd b7       	in	r28, 0x3d	; 61
 896:	de b7       	in	r29, 0x3e	; 62
 898:	18 2f       	mov	r17, r24
 89a:	06 2f       	mov	r16, r22
	unsigned char regvalue;

	lib_nRF24L01_read_register ( reg, &regvalue, 1);
 89c:	41 e0       	ldi	r20, 0x01	; 1
 89e:	be 01       	movw	r22, r28
 8a0:	6f 5f       	subi	r22, 0xFF	; 255
 8a2:	7f 4f       	sbci	r23, 0xFF	; 255
 8a4:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	regvalue |= bitmask;
 8a8:	99 81       	ldd	r25, Y+1	; 0x01
 8aa:	90 2b       	or	r25, r16
 8ac:	99 83       	std	Y+1, r25	; 0x01
	lib_nRF24L01_write_register( reg, &regvalue, 1);
 8ae:	41 e0       	ldi	r20, 0x01	; 1
 8b0:	be 01       	movw	r22, r28
 8b2:	6f 5f       	subi	r22, 0xFF	; 255
 8b4:	7f 4f       	sbci	r23, 0xFF	; 255
 8b6:	81 2f       	mov	r24, r17
 8b8:	0e 94 eb 03 	call	0x7d6	; 0x7d6 <lib_nRF24L01_write_register>
}
 8bc:	0f 90       	pop	r0
 8be:	df 91       	pop	r29
 8c0:	cf 91       	pop	r28
 8c2:	1f 91       	pop	r17
 8c4:	0f 91       	pop	r16
 8c6:	08 95       	ret

000008c8 <lib_nRF24L01_mask_IRQ>:
// 		nRF_REGBITMASK_CONFIG_MASK_TX_DS
// 		nRF_REGBITMASK_CONFIG_MASK_RX_DR
// 		nRF_REGBITMASK_CONFIG_MASK_MAX_RT
void lib_nRF24L01_mask_IRQ( uint8_t bitmask)
{
	lib_nRF24L01_set_regbits( nRF_REG_CONFIG, bitmask);
 8c8:	68 2f       	mov	r22, r24
 8ca:	80 e0       	ldi	r24, 0x00	; 0
 8cc:	0c 94 45 04 	jmp	0x88a	; 0x88a <lib_nRF24L01_set_regbits>

000008d0 <lib_nRF24L01_clear_IRQ>:


// resets IRQ flag(s) in the STATUS register
void lib_nRF24L01_clear_IRQ( uint8_t bitmask)
{
	lib_nRF24L01_set_regbits( nRF_REG_STATUS, bitmask);		// IRQ flags are reset by writing a logical 1 to their bit position
 8d0:	68 2f       	mov	r22, r24
 8d2:	87 e0       	ldi	r24, 0x07	; 7
 8d4:	0c 94 45 04 	jmp	0x88a	; 0x88a <lib_nRF24L01_set_regbits>

000008d8 <lib_nRF24L01_unset_regbits>:
	lib_nRF24L01_write_register( reg, &regvalue, 1);
}


void lib_nRF24L01_unset_regbits( uint8_t reg, uint8_t bitmask)
{
 8d8:	0f 93       	push	r16
 8da:	1f 93       	push	r17
 8dc:	cf 93       	push	r28
 8de:	df 93       	push	r29
 8e0:	1f 92       	push	r1
 8e2:	cd b7       	in	r28, 0x3d	; 61
 8e4:	de b7       	in	r29, 0x3e	; 62
 8e6:	18 2f       	mov	r17, r24
 8e8:	06 2f       	mov	r16, r22
	unsigned char regvalue;

	lib_nRF24L01_read_register ( reg, &regvalue, 1);
 8ea:	41 e0       	ldi	r20, 0x01	; 1
 8ec:	be 01       	movw	r22, r28
 8ee:	6f 5f       	subi	r22, 0xFF	; 255
 8f0:	7f 4f       	sbci	r23, 0xFF	; 255
 8f2:	0e 94 2f 03 	call	0x65e	; 0x65e <lib_nRF24L01_read_register>
	regvalue &= ~bitmask;
 8f6:	00 95       	com	r16
 8f8:	99 81       	ldd	r25, Y+1	; 0x01
 8fa:	90 23       	and	r25, r16
 8fc:	99 83       	std	Y+1, r25	; 0x01
	lib_nRF24L01_write_register( reg, &regvalue, 1);
 8fe:	41 e0       	ldi	r20, 0x01	; 1
 900:	be 01       	movw	r22, r28
 902:	6f 5f       	subi	r22, 0xFF	; 255
 904:	7f 4f       	sbci	r23, 0xFF	; 255
 906:	81 2f       	mov	r24, r17
 908:	0e 94 eb 03 	call	0x7d6	; 0x7d6 <lib_nRF24L01_write_register>
}
 90c:	0f 90       	pop	r0
 90e:	df 91       	pop	r29
 910:	cf 91       	pop	r28
 912:	1f 91       	pop	r17
 914:	0f 91       	pop	r16
 916:	08 95       	ret

00000918 <lib_nRF24L01_get_status>:

// return the value of the status register
uint8_t lib_nRF24L01_get_status()
{
	uint8_t status;
	lib_nRF24L01_EXECUTE(
 918:	5d 98       	cbi	0x0b, 5	; 11
 91a:	8f ef       	ldi	r24, 0xFF	; 255
 91c:	0e 94 20 02 	call	0x440	; 0x440 <spi_transfer_byte>
 920:	5d 9a       	sbi	0x0b, 5	; 11
		status = spi_fast_shift( nRF_CMD_NOP);
	)
	return status;
}
 922:	08 95       	ret

00000924 <lib_nRF24L01_get_rx_pipe_num>:
// Returns the RX data pipe number of the data currently available in the RX-FIFO to be read out.
// Returns -1, if there is no data available (empty RX-FIFO).
int8_t lib_nRF24L01_get_rx_pipe_num()
{
	uint8_t lib_nRF24L01_pipe_num;
	lib_nRF24L01_pipe_num = ( lib_nRF24L01_get_status() & nRF_REGBITMASK_STATUS_RX_P_NO ) >> nRF_REGBITSHIFT_STATUS_RX_P_NO;
 924:	0e 94 8c 04 	call	0x918	; 0x918 <lib_nRF24L01_get_status>
 928:	8e 70       	andi	r24, 0x0E	; 14
 92a:	90 e0       	ldi	r25, 0x00	; 0
 92c:	95 95       	asr	r25
 92e:	87 95       	ror	r24
	if ( lib_nRF24L01_pipe_num <= 5 )
 930:	86 30       	cpi	r24, 0x06	; 6
 932:	08 f0       	brcs	.+2      	; 0x936 <lib_nRF24L01_get_rx_pipe_num+0x12>
		return lib_nRF24L01_pipe_num;
	else	// lib_nRF24L01_pipe_num == ( nRF_REGVAL_STATUS_RX_P_NO_FIFO_EMPTY >> nRF_REGBITSHIFT_STATUS_RX_P_NO )
		return -1;
 934:	8f ef       	ldi	r24, 0xFF	; 255
}
 936:	08 95       	ret

00000938 <lib_nRF24L01_handle_interrupt>:
//				if ( lib_nRF24L01_IRQ_scheduled ) lib_nRF24L01_handle_interrupt();
//				...;
//			}
// If another/more functionality is needed by the application, the application needs to define its own interrupt handling function.
void lib_nRF24L01_handle_interrupt( void)
{
 938:	cf 93       	push	r28
	uint8_t status = lib_nRF24L01_get_status();
 93a:	0e 94 8c 04 	call	0x918	; 0x918 <lib_nRF24L01_get_status>
 93e:	c8 2f       	mov	r28, r24

	// packet successfully sent
	if ( status & nRF_REGBITMASK_STATUS_TX_DS )													
 940:	85 ff       	sbrs	r24, 5
 942:	03 c0       	rjmp	.+6      	; 0x94a <lib_nRF24L01_handle_interrupt+0x12>
	{
#ifdef DEBUG
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
#endif
		// no need to do anything but to reset the IRQ flag
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_TX_DS);
 944:	80 e2       	ldi	r24, 0x20	; 32
 946:	0e 94 68 04 	call	0x8d0	; 0x8d0 <lib_nRF24L01_clear_IRQ>
	}

	// packet received
	if ( status & nRF_REGBITMASK_STATUS_RX_DR )														
 94a:	c6 fd       	sbrc	r28, 6
 94c:	08 c0       	rjmp	.+16     	; 0x95e <lib_nRF24L01_handle_interrupt+0x26>
		while ( lib_nRF24L01_get_regbyte( nRF_REG_FIFO_STATUS) & nRF_REGBITMASK_STATUS_RX_DR )
			lib_nRF24L01_flush_RX_FIFO();
	}

	// maximum automatic retransmits reached -> packet not successfully sent
	if ( status & nRF_REGBITMASK_STATUS_MAX_RT )
 94e:	c4 ff       	sbrs	r28, 4
 950:	1d c0       	rjmp	.+58     	; 0x98c <lib_nRF24L01_handle_interrupt+0x54>
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
#endif
		// keep your mind free and just forget that this happened
		// § alternatively, CE could be toggled in order to trigger another transmission cycle
		lib_nRF24L01_flush_TX_FIFO();
 952:	0e 94 59 02 	call	0x4b2	; 0x4b2 <lib_nRF24L01_flush_TX_FIFO>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_MAX_RT);
 956:	80 e1       	ldi	r24, 0x10	; 16
 958:	0e 94 68 04 	call	0x8d0	; 0x8d0 <lib_nRF24L01_clear_IRQ>
 95c:	17 c0       	rjmp	.+46     	; 0x98c <lib_nRF24L01_handle_interrupt+0x54>
	{
#ifdef DEBUG
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
PORTC |= (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3); _delay_ms( 150);
#endif
		lib_nRF24L01_pipe_num = lib_nRF24L01_get_rx_pipe_num();		// store source and data in static variables
 95e:	0e 94 92 04 	call	0x924	; 0x924 <lib_nRF24L01_get_rx_pipe_num>
 962:	80 93 2b 01 	sts	0x012B, r24
		lib_nRF24L01_get_data( lib_nRF24L01_RX_data, nRF24L01_MAX_RX_PAYLOAD_LEN);		// § overwrites RX-data even if the main app has not processed it yet
 966:	60 e2       	ldi	r22, 0x20	; 32
 968:	8b e0       	ldi	r24, 0x0B	; 11
 96a:	91 e0       	ldi	r25, 0x01	; 1
 96c:	0e 94 02 03 	call	0x604	; 0x604 <lib_nRF24L01_get_data>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_RX_DR);
 970:	80 e4       	ldi	r24, 0x40	; 64
 972:	0e 94 68 04 	call	0x8d0	; 0x8d0 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_newDataAvailable = true;
 976:	81 e0       	ldi	r24, 0x01	; 1
 978:	80 93 2c 01 	sts	0x012C, r24
		// discard any other data received
		// §§ of course, the data should be stored as well, if needed
		while ( lib_nRF24L01_get_regbyte( nRF_REG_FIFO_STATUS) & nRF_REGBITMASK_STATUS_RX_DR )
 97c:	87 e1       	ldi	r24, 0x17	; 23
 97e:	0e 94 af 02 	call	0x55e	; 0x55e <lib_nRF24L01_get_regbyte>
 982:	86 ff       	sbrs	r24, 6
 984:	e4 cf       	rjmp	.-56     	; 0x94e <lib_nRF24L01_handle_interrupt+0x16>
			lib_nRF24L01_flush_RX_FIFO();
 986:	0e 94 5f 02 	call	0x4be	; 0x4be <lib_nRF24L01_flush_RX_FIFO>
 98a:	f8 cf       	rjmp	.-16     	; 0x97c <lib_nRF24L01_handle_interrupt+0x44>
		// § alternatively, CE could be toggled in order to trigger another transmission cycle
		lib_nRF24L01_flush_TX_FIFO();
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_MAX_RT);
	}
	
	lib_nRF24L01_IRQ_scheduled = false;								// pretend all is done
 98c:	10 92 2d 01 	sts	0x012D, r1
}
 990:	cf 91       	pop	r28
 992:	08 95       	ret

00000994 <lib_nRF24L01_data_ready>:


// Checks if RX data is available for reading
bool lib_nRF24L01_data_ready()
{
	return lib_nRF24L01_get_status() & nRF_REGBITMASK_STATUS_RX_DR;
 994:	0e 94 8c 04 	call	0x918	; 0x918 <lib_nRF24L01_get_status>
}
 998:	86 fb       	bst	r24, 6
 99a:	88 27       	eor	r24, r24
 99c:	80 f9       	bld	r24, 0
 99e:	08 95       	ret

000009a0 <lib_nRF24L01_set_tx_addr>:
//	addr_msbs
//		pointer to all bytes except the first one of the device address to be set
//	addr_lsb
//		first byte of the device address to be set
void lib_nRF24L01_set_tx_addr( uint8_t groupID, uint8_t deviceID)
{
 9a0:	cf 93       	push	r28
 9a2:	df 93       	push	r29
 9a4:	00 d0       	rcall	.+0      	; 0x9a6 <lib_nRF24L01_set_tx_addr+0x6>
 9a6:	1f 92       	push	r1
 9a8:	cd b7       	in	r28, 0x3d	; 61
 9aa:	de b7       	in	r29, 0x3e	; 62
	uint8_t address[lib_nRF24L01_ADDR_WIDTH];

	address[0] = deviceID;						// LSB first
 9ac:	69 83       	std	Y+1, r22	; 0x01
	address[1] = groupID;
 9ae:	8a 83       	std	Y+2, r24	; 0x02
	address[2] = lib_nRF24L01_ADDR_MSB;
 9b0:	82 e4       	ldi	r24, 0x42	; 66
 9b2:	8b 83       	std	Y+3, r24	; 0x03

	lib_nRF24L01_write_register( nRF_REG_TX_ADDR, address, lib_nRF24L01_ADDR_WIDTH);
 9b4:	43 e0       	ldi	r20, 0x03	; 3
 9b6:	be 01       	movw	r22, r28
 9b8:	6f 5f       	subi	r22, 0xFF	; 255
 9ba:	7f 4f       	sbci	r23, 0xFF	; 255
 9bc:	80 e1       	ldi	r24, 0x10	; 16
 9be:	0e 94 eb 03 	call	0x7d6	; 0x7d6 <lib_nRF24L01_write_register>
}
 9c2:	0f 90       	pop	r0
 9c4:	0f 90       	pop	r0
 9c6:	0f 90       	pop	r0
 9c8:	df 91       	pop	r29
 9ca:	cf 91       	pop	r28
 9cc:	08 95       	ret

000009ce <lib_nRF24L01_init_nRF24L01>:
//		mode		lib_nRF24L01_TXmode | lib_nRF24L01_RXmode
// 		groupID 	the middle byte of the address of the nRF24L01+. This lib uses this byte as common address part of a multiceiver-group.
// 		deviceID 	the LSByte of the address of the nRF24L01+. This lib uses default values from 1...6 for the transmitters of a multiceiver-group.
// 		rf_channel	RF frequency channel to use: F(RF) = 2400 + x [MHz], where x = 0..125
void lib_nRF24L01_init_nRF24L01( uint8_t mode, uint8_t groupID, uint8_t deviceID, uint8_t rf_channel)
{
 9ce:	ff 92       	push	r15
 9d0:	0f 93       	push	r16
 9d2:	1f 93       	push	r17
 9d4:	cf 93       	push	r28
 9d6:	df 93       	push	r29
 9d8:	1f 92       	push	r1
 9da:	cd b7       	in	r28, 0x3d	; 61
 9dc:	de b7       	in	r29, 0x3e	; 62
 9de:	18 2f       	mov	r17, r24
 9e0:	06 2f       	mov	r16, r22
 9e2:	f4 2e       	mov	r15, r20
	// the nRF24L01+ power on reset procedure needs 100ms after operating voltage is supplied
	if ( ! (currentState & STATE_BITMASK_INIT  ) )
 9e4:	80 91 02 01 	lds	r24, 0x0102
 9e8:	80 fd       	sbrc	r24, 0
 9ea:	09 c0       	rjmp	.+18     	; 0x9fe <lib_nRF24L01_init_nRF24L01+0x30>
 9ec:	3f ef       	ldi	r19, 0xFF	; 255
 9ee:	81 ee       	ldi	r24, 0xE1	; 225
 9f0:	94 e0       	ldi	r25, 0x04	; 4
 9f2:	31 50       	subi	r19, 0x01	; 1
 9f4:	80 40       	sbci	r24, 0x00	; 0
 9f6:	90 40       	sbci	r25, 0x00	; 0
 9f8:	e1 f7       	brne	.-8      	; 0x9f2 <lib_nRF24L01_init_nRF24L01+0x24>
 9fa:	00 c0       	rjmp	.+0      	; 0x9fc <lib_nRF24L01_init_nRF24L01+0x2e>
 9fc:	00 00       	nop
		_delay_us( nRF24L01_DELAY_POWERON_RESET);

	if (   (currentState & STATE_BITMASK_PWR_UP) )
 9fe:	80 91 02 01 	lds	r24, 0x0102
 a02:	81 ff       	sbrs	r24, 1
 a04:	11 c0       	rjmp	.+34     	; 0xa28 <lib_nRF24L01_init_nRF24L01+0x5a>
	{
		// flush all data pipes, reset all interrupt flags (IRQ-pin), then go down
		lib_nRF24L01_flush_TX_FIFO();
 a06:	29 83       	std	Y+1, r18	; 0x01
 a08:	0e 94 59 02 	call	0x4b2	; 0x4b2 <lib_nRF24L01_flush_TX_FIFO>
		lib_nRF24L01_flush_RX_FIFO();
 a0c:	0e 94 5f 02 	call	0x4be	; 0x4be <lib_nRF24L01_flush_RX_FIFO>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_TX_DS);
 a10:	80 e2       	ldi	r24, 0x20	; 32
 a12:	0e 94 68 04 	call	0x8d0	; 0x8d0 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_RX_DR);
 a16:	80 e4       	ldi	r24, 0x40	; 64
 a18:	0e 94 68 04 	call	0x8d0	; 0x8d0 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_clear_IRQ( nRF_REGBITMASK_STATUS_MAX_RT);
 a1c:	80 e1       	ldi	r24, 0x10	; 16
 a1e:	0e 94 68 04 	call	0x8d0	; 0x8d0 <lib_nRF24L01_clear_IRQ>
		lib_nRF24L01_power_down();
 a22:	0e 94 05 04 	call	0x80a	; 0x80a <lib_nRF24L01_power_down>
 a26:	29 81       	ldd	r18, Y+1	; 0x01
	}

	// Set RF channel
	lib_nRF24L01_set_regbyte( nRF_REG_RF_CH, rf_channel);
 a28:	62 2f       	mov	r22, r18
 a2a:	85 e0       	ldi	r24, 0x05	; 5
 a2c:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
	// Set data speed & Output Power configured in lib_nRF24L01.h
	lib_nRF24L01_set_regbyte( nRF_REG_RF_SETUP, lib_nRF24L01_RF_SETUP);
 a30:	66 e2       	ldi	r22, 0x26	; 38
 a32:	86 e0       	ldi	r24, 0x06	; 6
 a34:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>

	// Set Device Address Width
	lib_nRF24L01_set_regbyte( nRF_REG_SETUP_AW, nRF_REGBITVAL_SETUP_AW_3BYTES);
 a38:	61 e0       	ldi	r22, 0x01	; 1
 a3a:	83 e0       	ldi	r24, 0x03	; 3
 a3c:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
	
	// Set device addresses for a "multiceiver group" (a star topology consisting of 1 receiver and up to 6 transmitters) with auto acknowledge
	if ( mode == lib_nRF24L01_TXmode )
 a40:	11 30       	cpi	r17, 0x01	; 1
 a42:	41 f5       	brne	.+80     	; 0xa94 <lib_nRF24L01_init_nRF24L01+0xc6>
	{
		// Set Device Address (which identifies the transmitter)
		lib_nRF24L01_set_tx_addr( groupID, deviceID);
 a44:	6f 2d       	mov	r22, r15
 a46:	80 2f       	mov	r24, r16
 a48:	0e 94 d0 04 	call	0x9a0	; 0x9a0 <lib_nRF24L01_set_tx_addr>
		// Enable only RX data pipe 0 for receiving data (to receive acknowledge-packets from a listening receiver)
		lib_nRF24L01_set_regbyte( nRF_REG_EN_RXADDR, nRF_REGBITMASK_EN_RXADDR_ERX_P0);
 a4c:	61 e0       	ldi	r22, 0x01	; 1
 a4e:	82 e0       	ldi	r24, 0x02	; 2
 a50:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 a54:	4f 2d       	mov	r20, r15
 a56:	60 2f       	mov	r22, r16
 a58:	80 e0       	ldi	r24, 0x00	; 0
 a5a:	0e 94 26 04 	call	0x84c	; 0x84c <lib_nRF24L01_set_rx_addr.part.2>
 a5e:	4f ef       	ldi	r20, 0xFF	; 255
 a60:	6f ef       	ldi	r22, 0xFF	; 255
 a62:	81 e0       	ldi	r24, 0x01	; 1
 a64:	0e 94 26 04 	call	0x84c	; 0x84c <lib_nRF24L01_set_rx_addr.part.2>
		address[2] = lib_nRF24L01_ADDR_MSB;
		lib_nRF24L01_write_register( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, address, lib_nRF24L01_ADDR_WIDTH);
	}
	else										// data pipes 2..5 get only the deviceID assigned, because their MSBytes are the same as of data pipe 1
	{
		lib_nRF24L01_set_regbyte( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, deviceID);
 a68:	6f ef       	ldi	r22, 0xFF	; 255
 a6a:	8c e0       	ldi	r24, 0x0C	; 12
 a6c:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 a70:	6f ef       	ldi	r22, 0xFF	; 255
 a72:	8d e0       	ldi	r24, 0x0D	; 13
 a74:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 a78:	6f ef       	ldi	r22, 0xFF	; 255
 a7a:	8e e0       	ldi	r24, 0x0E	; 14
 a7c:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 a80:	6f ef       	ldi	r22, 0xFF	; 255
 a82:	8f e0       	ldi	r24, 0x0F	; 15
 a84:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
	// ... Automatic Retransmission
	//     Note 1: use nRF_REG_SETUP_RETR ARD setting faster than 500us with caution: read note (d) at the end of the Register Map Table (page 60 of manual)!
	//     Note 2: § in order to avoid repeated transmission collisions, ensure different values for each device working on the same RF-channel
	if ( mode == lib_nRF24L01_TXmode )
	{
		uint8_t delay = (0x10 * (1+deviceID)) & nRF_REGBITMASK_SETUP_RETR_ARD;		// see nRF_REGVAL_SETUP_RETR_ARD_*-constants
 a88:	6f 2d       	mov	r22, r15
 a8a:	62 95       	swap	r22
 a8c:	60 7f       	andi	r22, 0xF0	; 240
 a8e:	60 5f       	subi	r22, 0xF0	; 240
		lib_nRF24L01_set_regbyte( nRF_REG_SETUP_RETR, (delay | nRF_REGVAL_SETUP_RETR_ARC_15) );
 a90:	6f 60       	ori	r22, 0x0F	; 15
 a92:	28 c0       	rjmp	.+80     	; 0xae4 <lib_nRF24L01_init_nRF24L01+0x116>
	}
	else	// i.e. mode == lib_nRF24L01_RXmode (multiceiver)
	{
		// In order to avoid address conflicts which could occur when the PRX is switched to TX mode on the fly,
		// the Device Address is set even in RX-mode
		lib_nRF24L01_set_tx_addr(    groupID, deviceID > 6 ? deviceID : 0);		// ensure the deviceID does not collide with one of the transmitters of the same group
 a94:	e6 e0       	ldi	r30, 0x06	; 6
 a96:	ef 15       	cp	r30, r15
 a98:	10 f0       	brcs	.+4      	; 0xa9e <lib_nRF24L01_init_nRF24L01+0xd0>
 a9a:	60 e0       	ldi	r22, 0x00	; 0
 a9c:	01 c0       	rjmp	.+2      	; 0xaa0 <lib_nRF24L01_init_nRF24L01+0xd2>
 a9e:	6f 2d       	mov	r22, r15
 aa0:	80 2f       	mov	r24, r16
 aa2:	0e 94 d0 04 	call	0x9a0	; 0x9a0 <lib_nRF24L01_set_tx_addr>
		// Enable all RX data pipe addresses for receiving data
		lib_nRF24L01_set_regbyte( nRF_REG_EN_RXADDR, nRF_REGBITMASK_EN_RXADDR_ERX_ALL);
 aa6:	6f e3       	ldi	r22, 0x3F	; 63
 aa8:	82 e0       	ldi	r24, 0x02	; 2
 aaa:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 aae:	41 e0       	ldi	r20, 0x01	; 1
 ab0:	60 2f       	mov	r22, r16
 ab2:	80 e0       	ldi	r24, 0x00	; 0
 ab4:	0e 94 26 04 	call	0x84c	; 0x84c <lib_nRF24L01_set_rx_addr.part.2>
 ab8:	42 e0       	ldi	r20, 0x02	; 2
 aba:	60 2f       	mov	r22, r16
 abc:	81 e0       	ldi	r24, 0x01	; 1
 abe:	0e 94 26 04 	call	0x84c	; 0x84c <lib_nRF24L01_set_rx_addr.part.2>
		address[2] = lib_nRF24L01_ADDR_MSB;
		lib_nRF24L01_write_register( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, address, lib_nRF24L01_ADDR_WIDTH);
	}
	else										// data pipes 2..5 get only the deviceID assigned, because their MSBytes are the same as of data pipe 1
	{
		lib_nRF24L01_set_regbyte( nRF_REG_RX_ADDR_P0 + lib_nRF24L01_pipe_num, deviceID);
 ac2:	63 e0       	ldi	r22, 0x03	; 3
 ac4:	8c e0       	ldi	r24, 0x0C	; 12
 ac6:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 aca:	64 e0       	ldi	r22, 0x04	; 4
 acc:	8d e0       	ldi	r24, 0x0D	; 13
 ace:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 ad2:	65 e0       	ldi	r22, 0x05	; 5
 ad4:	8e e0       	ldi	r24, 0x0E	; 14
 ad6:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
 ada:	66 e0       	ldi	r22, 0x06	; 6
 adc:	8f e0       	ldi	r24, 0x0F	; 15
 ade:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
		uint8_t delay = (0x10 * (1+deviceID)) & nRF_REGBITMASK_SETUP_RETR_ARD;		// see nRF_REGVAL_SETUP_RETR_ARD_*-constants
		lib_nRF24L01_set_regbyte( nRF_REG_SETUP_RETR, (delay | nRF_REGVAL_SETUP_RETR_ARC_15) );
	}
	else
	{
		lib_nRF24L01_set_regbyte( nRF_REG_SETUP_RETR, (nRF_REGVAL_SETUP_RETR_ARD_500 | nRF_REGVAL_SETUP_RETR_ARC_15) );
 ae2:	6f e1       	ldi	r22, 0x1F	; 31
 ae4:	84 e0       	ldi	r24, 0x04	; 4
 ae6:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
	}
	// ... Dynamic Payload Length as well as Automatic Acknowledgement Payloads
	lib_nRF24L01_set_regbyte( nRF_REG_FEATURE,   nRF_REGBITMASK_FEATURE_EN_DPL			// enables Dynamic Payload Length
 aea:	67 e0       	ldi	r22, 0x07	; 7
 aec:	8d e1       	ldi	r24, 0x1D	; 29
 aee:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
											   | nRF_REGBITMASK_FEATURE_EN_DYN_ACK		// enables use of nRF_CMD_W_TX_PAYLOAD_NOACK command
											   | nRF_REGBITMASK_FEATURE_EN_ACK_PAY		// enables "Acknowledge Payloads"
							);
	// ... enable Automatic Acknowledgement for all data pipes
	lib_nRF24L01_set_regbyte( nRF_REG_EN_AA, nRF_REGBITMASK_EN_AA_ENAA_ALL);
 af2:	6f e3       	ldi	r22, 0x3F	; 63
 af4:	81 e0       	ldi	r24, 0x01	; 1
 af6:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>
	// ... enable Dynamic Payload Length for all data pipes
	lib_nRF24L01_set_regbyte( nRF_REG_DYNPD, nRF_REGBITMASK_DYNPD_ALL);
 afa:	6f e3       	ldi	r22, 0x3F	; 63
 afc:	8c e1       	ldi	r24, 0x1C	; 28
 afe:	0e 94 c5 02 	call	0x58a	; 0x58a <lib_nRF24L01_set_regbyte>

	currentState = STATE_BITMASK_INIT;						// initialised, powered down
 b02:	81 e0       	ldi	r24, 0x01	; 1
 b04:	80 93 02 01 	sts	0x0102, r24
}
 b08:	0f 90       	pop	r0
 b0a:	df 91       	pop	r29
 b0c:	cf 91       	pop	r28
 b0e:	1f 91       	pop	r17
 b10:	0f 91       	pop	r16
 b12:	ff 90       	pop	r15
 b14:	08 95       	ret

00000b16 <lib_nRF24L01_init>:
//-----------------------------------------------------------------------------
// initialising
//-----------------------------------------------------------------------------

void lib_nRF24L01_init( uint8_t mode, uint8_t groupID, uint8_t deviceID, uint8_t rf_channel)
{
 b16:	cf 93       	push	r28
 b18:	df 93       	push	r29
 b1a:	00 d0       	rcall	.+0      	; 0xb1c <lib_nRF24L01_init+0x6>
 b1c:	00 d0       	rcall	.+0      	; 0xb1e <lib_nRF24L01_init+0x8>
 b1e:	cd b7       	in	r28, 0x3d	; 61
 b20:	de b7       	in	r29, 0x3e	; 62
	lib_nRF24L01_init_MCU();
 b22:	2c 83       	std	Y+4, r18	; 0x04
 b24:	4b 83       	std	Y+3, r20	; 0x03
 b26:	6a 83       	std	Y+2, r22	; 0x02
 b28:	89 83       	std	Y+1, r24	; 0x01
 b2a:	0e 94 77 02 	call	0x4ee	; 0x4ee <lib_nRF24L01_init_MCU>
	lib_nRF24L01_init_nRF24L01( mode, groupID, deviceID, rf_channel);
 b2e:	2c 81       	ldd	r18, Y+4	; 0x04
 b30:	4b 81       	ldd	r20, Y+3	; 0x03
 b32:	6a 81       	ldd	r22, Y+2	; 0x02
 b34:	89 81       	ldd	r24, Y+1	; 0x01
 b36:	0e 94 e7 04 	call	0x9ce	; 0x9ce <lib_nRF24L01_init_nRF24L01>
	lib_nRF24L01_IRQ_scheduled = false;
 b3a:	10 92 2d 01 	sts	0x012D, r1
}
 b3e:	0f 90       	pop	r0
 b40:	0f 90       	pop	r0
 b42:	0f 90       	pop	r0
 b44:	0f 90       	pop	r0
 b46:	df 91       	pop	r29
 b48:	cf 91       	pop	r28
 b4a:	08 95       	ret

00000b4c <lib_nRF24L01_set_rx_addr>:
//		first byte of the device address to be set
void lib_nRF24L01_set_rx_addr( uint8_t lib_nRF24L01_pipe_num, uint8_t groupID, uint8_t deviceID)
{
	uint8_t address[lib_nRF24L01_ADDR_WIDTH];
	
	if ( lib_nRF24L01_pipe_num > 5 )
 b4c:	86 30       	cpi	r24, 0x06	; 6
 b4e:	10 f4       	brcc	.+4      	; 0xb54 <lib_nRF24L01_set_rx_addr+0x8>
 b50:	0c 94 26 04 	jmp	0x84c	; 0x84c <lib_nRF24L01_set_rx_addr.part.2>
 b54:	08 95       	ret

00000b56 <main>:


int main( void)
{
 b56:	cf 93       	push	r28
 b58:	df 93       	push	r29
 b5a:	00 d0       	rcall	.+0      	; 0xb5c <main+0x6>
 b5c:	cd b7       	in	r28, 0x3d	; 61
 b5e:	de b7       	in	r29, 0x3e	; 62
	uint16_t wdt_counter = 0;										// counts the number of times the MCU awakes by a watchdog interrupt
	uint8_t  sensordata[2];											// [0] humidity, [1] temperature

	// LED port pin
	PORTC &= ~(1<<PC3);
 b60:	43 98       	cbi	0x08, 3	; 8
	DDRC  |=  (1<<PC3);
 b62:	3b 9a       	sbi	0x07, 3	; 7

	// transmitter module
	lib_nRF24L01_init( lib_nRF24L01_TXmode, 69, 1, 42);				// mode, groupID (arbitrary), deviceID (1..6), rf_channel (0..125)
 b64:	2a e2       	ldi	r18, 0x2A	; 42
 b66:	41 e0       	ldi	r20, 0x01	; 1
 b68:	65 e4       	ldi	r22, 0x45	; 69
 b6a:	81 e0       	ldi	r24, 0x01	; 1
 b6c:	0e 94 8b 05 	call	0xb16	; 0xb16 <lib_nRF24L01_init>
	lib_nRF24L01_invoke_TX_mode();									// note: starts the RF oscillator but not the RF power amp
 b70:	0e 94 ed 02 	call	0x5da	; 0x5da <lib_nRF24L01_invoke_TX_mode>

	// watchdog sleep-timer
	setupWatchdogInterrupt();
 b74:	0e 94 53 00 	call	0xa6	; 0xa6 <setupWatchdogInterrupt>
	set_sleep_mode( SLEEP_MODE_PWR_DOWN);
 b78:	83 b7       	in	r24, 0x33	; 51
 b7a:	81 7f       	andi	r24, 0xF1	; 241
 b7c:	84 60       	ori	r24, 0x04	; 4
 b7e:	83 bf       	out	0x33, r24	; 51
	uint8_t xxx = 0;
 b80:	10 e0       	ldi	r17, 0x00	; 0
		{
			wdt_counter = ACTION_INTERVAL >= WDT_INTERVAL ? ACTION_INTERVAL / WDT_INTERVAL - 1
														  : 0;

			// flash LED
			PORTC |=  (1<<PC3); _delay_ms( 5); PORTC &= ~(1<<PC3);
 b82:	43 9a       	sbi	0x08, 3	; 8
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 b84:	8f e1       	ldi	r24, 0x1F	; 31
 b86:	9e e4       	ldi	r25, 0x4E	; 78
 b88:	01 97       	sbiw	r24, 0x01	; 1
 b8a:	f1 f7       	brne	.-4      	; 0xb88 <main+0x32>
 b8c:	00 c0       	rjmp	.+0      	; 0xb8e <main+0x38>
 b8e:	00 00       	nop
 b90:	43 98       	cbi	0x08, 3	; 8
			
			// measurement
			acquire_DHT();											// note: the DHT11 should not be acquired a) within 1s after power on and b) more then once per second
 b92:	0e 94 ba 00 	call	0x174	; 0x174 <acquire_DHT>
			sensordata[0] = get_humidity();
 b96:	0e 94 01 02 	call	0x402	; 0x402 <get_humidity>
 b9a:	89 83       	std	Y+1, r24	; 0x01
			sensordata[1] = get_temperature();
 b9c:	0e 94 0a 02 	call	0x414	; 0x414 <get_temperature>
			sensordata[1] = xxx++;
 ba0:	01 e0       	ldi	r16, 0x01	; 1
 ba2:	01 0f       	add	r16, r17
 ba4:	1a 83       	std	Y+2, r17	; 0x02
			
			// send data
			if ( lib_nRF24L01_IRQ_scheduled )
 ba6:	80 91 2d 01 	lds	r24, 0x012D
 baa:	81 11       	cpse	r24, r1
				lib_nRF24L01_handle_interrupt();
 bac:	0e 94 9c 04 	call	0x938	; 0x938 <lib_nRF24L01_handle_interrupt>
			lib_nRF24L01_send( sensordata, 2);
 bb0:	62 e0       	ldi	r22, 0x02	; 2
 bb2:	ce 01       	movw	r24, r28
 bb4:	01 96       	adiw	r24, 0x01	; 1
 bb6:	0e 94 90 03 	call	0x720	; 0x720 <lib_nRF24L01_send>
		}

		// goto sleep mode with minimal current draw, after watchdog awakening services are switched on again
		lib_nRF24L01_power_down();
 bba:	0e 94 05 04 	call	0x80a	; 0x80a <lib_nRF24L01_power_down>
		spi_stop();
 bbe:	0e 94 1c 02 	call	0x438	; 0x438 <spi_stop>
		lib_nRF24L01_start();										// mode, groupID (arbitrary), deviceID (1..6), rf_channel (0..125)
 bc2:	0e 94 96 02 	call	0x52c	; 0x52c <lib_nRF24L01_start>
		sei();														// ensure interrupts are enabled, otherwise the MCU will go into eternal sleep
 bc6:	78 94       	sei
		sleep_mode();												// go to sleep now and wait for watchdog interrupt
 bc8:	83 b7       	in	r24, 0x33	; 51
 bca:	81 60       	ori	r24, 0x01	; 1
 bcc:	83 bf       	out	0x33, r24	; 51
 bce:	88 95       	sleep
 bd0:	83 b7       	in	r24, 0x33	; 51
 bd2:	8e 7f       	andi	r24, 0xFE	; 254
 bd4:	83 bf       	out	0x33, r24	; 51
		spi_init();													// §§ if lib_nRF24L01_init() selects special SPI properties, just calling spi_init() here will not be enough
 bd6:	0e 94 13 02 	call	0x426	; 0x426 <spi_init>
		lib_nRF24L01_invoke_TX_mode();
 bda:	0e 94 ed 02 	call	0x5da	; 0x5da <lib_nRF24L01_invoke_TX_mode>
	}
 bde:	10 2f       	mov	r17, r16
 be0:	d0 cf       	rjmp	.-96     	; 0xb82 <main+0x2c>

00000be2 <_exit>:
 be2:	f8 94       	cli

00000be4 <__stop_program>:
 be4:	ff cf       	rjmp	.-2      	; 0xbe4 <__stop_program>