//////////////////////RAM MODULE///////////////////////////
module input_ram (en, addr, data);
// input clk;
input en;
input [6:0] addr;
output reg [7:0] data;
always @(*)
begin
if (en)
begin
case(addr)
7'b000: data = 8'b00110001;
7'b001: data = 8'b00010000;
7'b010: data = 8'b00100000;
7'b011: data = 8'b11101101;
7'b100: data = 8'b11100011;
7'b101: data = 8'b00110011;
7'b110: data = 8'b11110111;
7'b111: data = 8'b00111011;
7'b1000: data = 8'b00110001;
7'b1001: data = 8'b00010000;
7'b1010: data = 8'b00100000;
7'b1011: data = 8'b11101101;
7'b1100: data = 8'b11100011;
7'b1101: data = 8'b00110011;
7'b1110: data = 8'b11110111;
7'b1111: data = 8'b00111011;
7'b10000: data = 8'b00110001;
7'b10001: data = 8'b00010000;
7'b10010: data = 8'b00100000;
7'b10011: data = 8'b11101101;
7'b10100: data = 8'b11100011;
7'b10101: data = 8'b00110011;
7'b10110: data = 8'b11110111;
7'b10111: data = 8'b00111011;
7'b11000: data = 8'b00110001;
7'b11001: data = 8'b00010000;
7'b11010: data = 8'b00100000;
7'b11011: data = 8'b11101101;
7'b11100: data = 8'b11100011;
7'b11101: data = 8'b00110011;
7'b11110: data = 8'b11110111;
7'b11111: data = 8'b00111011;
7'b100000: data = 8'b00110001;
7'b100001: data = 8'b00010000;
7'b100010: data = 8'b00100000;
7'b100011: data = 8'b11101101;
7'b100100: data = 8'b11100011;
7'b100101: data = 8'b00110011;
7'b100110: data = 8'b11110111;
7'b100111: data = 8'b00111011;
7'b101000: data = 8'b00110001;
7'b101001: data = 8'b00010000;
7'b101010: data = 8'b00100000;
7'b101011: data = 8'b11101101;
7'b101100: data = 8'b11100011;
7'b101101: data = 8'b00110011;
7'b101110: data = 8'b11110111;
7'b101111: data = 8'b00111011;
7'b110000: data = 8'b00110001;
7'b110001: data = 8'b00010000;
7'b110010: data = 8'b00100000;
7'b110011: data = 8'b11101101;
7'b110100: data = 8'b11100011;
7'b110101: data = 8'b00110011;
7'b110110: data = 8'b11110111;
7'b110111: data = 8'b00111011;
7'b111000: data = 8'b00110001;
7'b111001: data = 8'b00010000;
7'b111010: data = 8'b00100000;
7'b111011: data = 8'b11101101;
7'b111100: data = 8'b11100011;
7'b111101: data = 8'b00110011;
7'b111110: data = 8'b11110111;
7'b111111: data = 8'b00111011;
7'b1000000: data = 8'b00110001;
default: data = 8'b0000_XXXX;
endcase
end
end
endmodule
//////////////another rom module in which weight is stored/////////////
module weight_ram (en, addr, weight);
// input clk;
input en;
input [6:0] addr;
output reg [7:0] weight;
always @(* )
begin
if (en)
begin
case(addr)
7'b000: weight = 8'b11111011;
7'b001: weight = 8'b00001110;
7'b010: weight = 8'b11100000;
7'b011: weight = 8'b11110011;
7'b100: weight = 8'b11110011;
7'b101: weight = 8'b11100110;
7'b110: weight = 8'b11101100;
7'b111: weight = 8'b11110110;
7'b1000: weight = 8'b11111001;
7'b1001: weight = 8'b00000010;
7'b1010: weight = 8'b11111011;
7'b1011: weight = 8'b00001100;
7'b1100: weight = 8'b11101101;
7'b1101: weight = 8'b00011000;
7'b1110: weight = 8'b11100010;
7'b1111: weight = 8'b00001011;
7'b10000: weight = 8'b11111011;
7'b10001: weight = 8'b00000100;
7'b10010: weight = 8'b11101001;
7'b10011: weight = 8'b11101101;
7'b10100: weight = 8'b00010011;
7'b10101: weight = 8'b00011110;
7'b10110: weight = 8'b11110100;
7'b10111: weight = 8'b00001100;
7'b11000: weight = 8'b00011000;
7'b11001: weight = 8'b00011001;
7'b11010: weight = 8'b11100101;
7'b11011: weight = 8'b11100010;
7'b11100: weight = 8'b11101011;
7'b11101: weight = 8'b00011000;
7'b11110: weight = 8'b11100110;
7'b11111: weight = 8'b11111011;
7'b100000: weight = 8'b00011101;
7'b100001: weight = 8'b00000010;
7'b100010: weight = 8'b00001100;
7'b100011: weight = 8'b11110100;
7'b100100: weight = 8'b00001100;
7'b100101: weight = 8'b00010101;
7'b100110: weight = 8'b11100001;
7'b100111: weight = 8'b00010000;
7'b101000: weight = 8'b00011111;
7'b101001: weight = 8'b00010000;
7'b101010: weight = 8'b11110010;
7'b101011: weight = 8'b00010011;
7'b101100: weight = 8'b11100111;
7'b101101: weight = 8'b11111101;
7'b101110: weight = 8'b00011010;
7'b101111: weight = 8'b11110011;
7'b110000: weight = 8'b11110010;
7'b110001: weight = 8'b11101000;
7'b110010: weight = 8'b11100001;
7'b110011: weight = 8'b00001011;
7'b110100: weight = 8'b11101110;
7'b110101: weight = 8'b11110001;
7'b110110: weight = 8'b11111111;
7'b110111: weight = 8'b11100011;
7'b111000: weight = 8'b00000101;
7'b111001: weight = 8'b11101001;
7'b111010: weight = 8'b00000110;
7'b111011: weight = 8'b00001101;
7'b111100: weight = 8'b11100111;
7'b111101: weight = 8'b11111010;
7'b111110: weight = 8'b00001100;
7'b111111: weight = 8'b11111011;
7'b1000000: weight = 8'b11100011;
7'b1000001: weight = 8'b00000010;
7'b1000010: weight = 8'b00001010;
7'b1000011: weight = 8'b00000001;
7'b1000100: weight = 8'b00011100;
7'b1000101: weight = 8'b00000110;
7'b1000110: weight = 8'b00011010;
7'b1000111: weight = 8'b11101001;
default: weight = 8'b0000_XXXX;
endcase
end
end
endmodule
/////////////////Booth multiplier Multiplier to multiply data and weight
////////////////
module multiplier(prod, busy, mc, mp, clk, start);
output [15:0] prod;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
reg Q_1;
reg [3:0] count;
wire [7:0] sum, difference;
always @(posedge clk)
begin
if (start) begin
A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;
count <= 4'b0;
end
else
begin
case ({Q[0], Q_1})
2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
default: {A, Q, Q_1} <= {A[7], A, Q};
endcase
count <= count + 1'b1;
end
end
alu adder (sum, A, M, 1'b0);
alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q};
assign busy = (count < 8);
//assign temp = ((busy==0 && clk ==1) ? prod : 16'bx);
initial
begin
$monitor($time,"prod=%b, busy==%b, mc=%b, mp=%b, clk=%b, start=%b",prod,
busy, mc, mp, clk, start);
end
endmodule
//The following is an alu.
//It is an adder, but capable of subtraction:
//Recall that subtraction means adding the two's complement--
//a - b = a + (-b) = a + (inverted b + 1)
//The 1 will be coming in as cin (carry-in)
module alu(out, a, b, cin);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
////////////////////////////////////Testbench///////////////////////
module top_tst;
// Inputs
reg clk;
reg en;
reg start;
reg [6:0] address;
// reg [15:0] temp;
// Outputs
wire [15:0] mux_out,multiplied;
wire [7:0] data;
wire [7:0] weight;
wire busy;
// Instantiate the Unit Under Test (UUT)
top_module uut (
// .multiplied(multiplied),
.mux_out(mux_out),
.data(data),
.weight(weight),
.clk(clk),
.en(en),
.start(start),
.address(address),
.busy(busy)
);
initial
begin
clk = 0;
en = 0;
address = 7'b0;
en=1;
$monitor
($time,"clk=%b,en=%b,start=%b,address=%b,data=%b,weight=%b",clk,en,start
,address,data,weight);
end
always #2 clk=~clk;
always @ (data or weight)
begin
start=1;
#4 start=0;
end
always @ (busy==0)
begin
address=address+7'b1;
end
endmodule
Sir i am new to verilog and and i am getting problem while simulation
help me to come out from this situation
i will explain the scenario of my code
data and weight are two input which is stored in rom at different
address
and i used booth multiplier because some of my input are signed and what
i am doing that at adress=0000000 my data and weight load on dataline
and after multiplying when my answer of multipier is available i want to
increase my adress=0000001 so that next data and weight must be
available and process repeate but dont know where i am doing mistake in
test bench sir please help me to come out this problem
Attached files:
-
simulation.jpg
(170 KB)
