library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.rijndael_package.all; entity aes_main is port (state: in STD_LOGIC_VECTOR(127 downto 0); clk: in std_logic; roundkey: in STD_LOGIC_VECTOR(127 downto 0); rst: in std_logic; e1 : in STD_LOGIC; e2 : in STD_LOGIC; gclk : out STD_LOGIC; cypher:out STD_LOGIC_VECTOR(127 downto 0); DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end entity aes_main; architecture top_aes_RTL of aes_main is --byte substitution component byte_sub is port (state: in STD_LOGIC_VECTOR(7 downto 0); clk: in std_logic; rst: in std_logic; e1 : in STD_LOGIC; e2 : in STD_LOGIC; b: out STD_LOGIC_VECTOR(7 downto 0)); end component; --shift row component shift_row is port (state: in STD_LOGIC_VECTOR(127 downto 0); clk: in std_logic; rst: in std_logic; e1 : in STD_LOGIC; e2 : in STD_LOGIC; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end component; --mix column component mix_column is port (state: in STD_LOGIC_VECTOR(127 downto 0); clk: in std_logic; rst: in std_logic; e1 : in STD_LOGIC; e2 : in STD_LOGIC; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end component mix_column; --key generation component key_gen is port (roundkey: in STD_LOGIC_VECTOR(127 downto 0); round: in round_type; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end component; -- add round key component ADD_ROUNDKEY is port (state : STD_LOGIC_VECTOR(127 downto 0); roundkey : in STD_LOGIC_VECTOR(127 downto 0); clk: in std_logic; rst: in std_logic; e1 : in STD_LOGIC; e2 : in STD_LOGIC; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end component ADD_ROUNDKEY; ---- inverse byte substitution --component inv_byte_sub is --port (state: IN STD_LOGIC_VECTOR(7 downto 0); --clk: in std_logic; rst: in std_logic; --e1 : in STD_LOGIC; -- e2 : in STD_LOGIC; --b: out STD_LOGIC_VECTOR(7 downto 0)); --end component; -- ----inverse shift row --component inv_shift_row is --port (state: in STD_LOGIC_VECTOR(127 downto 0); --clk: in std_logic; rst: in std_logic; --e1 : in STD_LOGIC; -- e2 : in STD_LOGIC; --DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); --end component; ----inverse mix column --component inv_mix_column is --port (state: in STD_LOGIC_VECTOR(127 downto 0); --clk: in std_logic; rst: in std_logic; --e1 : in STD_LOGIC; -- e2 : in STD_LOGIC; --DATAOUT : out STD_LOGIC_VECTOR(127 downto 0)); --end component; -- signal a1,b1,gclock,c1 : STD_LOGIC; signal a2,data1 , data2, data3 , data4 , data5 , data6 , data7 , data8 , data9 , data10 , data11 , data12 , data13 , data14 , data15 , data16, data17 , data18, data19 , data20 , data21 , data22 , data23 , data24 , data25 , data26 , data27,data28,data29,data30 , data31,data32 : STD_LOGIC_VECTOR(7 downto 0); signal da,k,dataout1,dataout2,dataout3,dataout4,data,roundkey1,cypher1,cypher2,dataout5,dataout6,dataout7, dataout8,dataout9,dataout10,roundkey2: STD_LOGIC_VECTOR(127 downto 0); signal round : integer range 0 to 16; --signal i : integer range 0 to 16; -- round 0 begin a1 <= e1 or e2; process (clk,a1) begin if(clk'event and clk = '0') then b1 <= a1; else b1 <= b1; end if; end process; gclock <= clk and b1; gclk <= gclock; m1 : ADD_ROUNDKEY Port map ( state,roundkey,gclock,rst,e1,e2,cypher1); -- round 1 to 9 a1 <= e1 or e2; process (clk,a1) begin if(clk'event and clk = '0') then b1 <= a1; else b1 <= b1; end if; end process; gclock <= clk and b1; gclk <= gclock; k<=roundkey; GEN_1: for i in 0 to 8 generate A17 : byte_sub Port map (cypher1(127 downto 120),gclock,rst,e1,e2,data1); A18 : byte_sub Port map (cypher1(119 downto 112),gclock,rst,e1,e2,data2); A3 : byte_sub Port map (cypher1(111 downto 104),gclock,rst,e1,e2,data3); A4 : byte_sub Port map (cypher1(103 downto 96),gclock,rst,e1,e2,data4); A5 : byte_sub Port map (cypher1(95 downto 88),gclock,rst,e1,e2,data5); A6 : byte_sub Port map (cypher1(87 downto 80),gclock,rst,e1,e2,data6); A7 : byte_sub Port map (cypher1(79 downto 72),gclock,rst,e1,e2,data7); A8 : byte_sub Port map (cypher1(71 downto 64),gclock,rst,e1,e2,data8); A9 : byte_sub Port map (cypher1(63 downto 56),gclock,rst,e1,e2,data9); A10 : byte_sub Port map (cypher1(55 downto 48),gclock,rst,e1,e2,data10); A11 : byte_sub Port map (cypher1(47 downto 40),gclock,rst,e1,e2,data11); A12 : byte_sub Port map (cypher1(39 downto 32),gclock,rst,e1,e2,data12); A13 : byte_sub Port map (cypher1(31 downto 24),gclock,rst,e1,e2,data13); A14 : byte_sub Port map (cypher1(23 downto 16),gclock,rst,e1,e2,data14); A15 : byte_sub Port map (cypher1(15 downto 8),gclock,rst,e1,e2,data15); A16 : byte_sub Port map (cypher1(7 downto 0),gclock,rst,e1,e2,data16); data <= data1 & data2 & data3 & data4 & data5 & data6 & data7 & data8 & data9 & data10 & data11 & data12 & data13 & data14 & data15 & data16; Q1 : shift_row Port map (data,gclock,rst,e1,e2,dataout1); Q2 : mix_column Port map (dataout1,gclock,rst,e1,e2,dataout2); Q3 : key_gen Port map (k,i+1,roundkey1); Q4 : ADD_ROUNDKEY Port map ( roundkey1,dataout2,gclock,rst,e1,e2,cypher); cypher1 <= cypher; k <= roundkey1; cypher <= cypher1; end generate GEN_1; end architecture;