modulo 100 VHDL

Matlabo wrote:

Any help is deeply appreciated.

Do you have a working test bench for that design?

I made one and it does not schow anything making any kind of sense to me...

Matlabo wrote:

P.S2: I am running the simulation on ISE and it takes too much time. Any tips in order to reduce the simulation time ?

You must speed up your clock enables:

1

architecture Behavioral of diviseur is

2

:

3

    elsif rising_edge (Clk) then 

4

--      if qt=50000000 then 

5

      if qt=4999 then 

6

        enlh <='1' ;

7

:

8

--      if qt100 = 500000 then 

9

      if qt100 = 49 then 

10

        en100h <= '1';

11

:

12

  end process;

13

end Behavioral;

50000000 ... 500000

The usual "off-by-one" problem: with a compare value of 500000 you count 500001 clock cycles. Considering that it is very crude to handle the ones and hundreds by two separate prescalers:

1

    elsif rising_edge (Clk) then 

2

      if qt=50000000 then 

3

        enlh <='1' ;

4

        qt := 0;

5

      else enlh <= '0' ;

6

        qt := qt+1 ;

7

      end if;

8

9

      if qt100 = 500000 then 

10

        en100h <= '1';

11

        qt100 := 0;

12

      else

13

        qt100 := qt100 + 1;

14

      end if;

15

16

17

    end if;

Why don't you handle the digits in a way every "usual" counter does: when the ones reach 9, then with the next clock the tens are incremented and the ones are reset to 0. When the tens reach 9 then with the next clock the hundreds are incremented and the tens are reset. And so on...

Have a look at the code of the stop watch there: http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html

Its German, try Google translator.

BTW:

1

use IEEE. numeric_STD.ALL;

2

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Never ever both of them together! The numeric_std has all you need. With both of them you will now and then encounter weird error messages due to double definitions of some data types.