LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_counter_Leds IS
END tb_counter_Leds;
 
ARCHITECTURE behavior OF tb_counter_Leds IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Top_counter_7Seg_mod100
    PORT(
         reset : IN  std_logic;
         clk : IN  std_logic;
         CD : IN  std_logic;
         L : IN  std_logic;
         E : IN INTEGER RANGE 0 TO 9;
         Choix_Afficheur : OUT  std_logic_vector(3 downto 0);
         Coded_7seg_Nb : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal reset : std_logic := '0';
   signal clk : std_logic := '0';
   signal CD : std_logic := '1';
   signal L : std_logic := '1';
   signal E : INTEGER RANGE 0 TO 9 := 1;

 	--Outputs
   signal Choix_Afficheur : std_logic_vector(3 downto 0);
   signal Coded_7seg_Nb : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Top_counter_7Seg_mod100 PORT MAP (
          reset => reset,
          clk => clk,
          CD => CD,
          L => L,
          E => E,
          Choix_Afficheur => Choix_Afficheur,
          Coded_7seg_Nb => Coded_7seg_Nb
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 50 ns;	
      reset <= '1';
      wait for 50 ns;
      reset <= '0';

      -- insert stimulus here 

      wait;
   end process;

END;