library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;        -- for addition & counting
use ieee.numeric_std.all;               -- for type conversions


entity Bin_2_BCD is
port(  Q    : in std_logic_vector(3 downto 0);
	   co   : in STD_LOGIC;
	   unit : out std_logic_vector(3 downto 0);
	   diz  : out std_logic_vector(3 downto 0) := "0000"
	);
end Bin_2_BCD;

architecture Behavioral of Bin_2_BCD is

	signal compteur_diz : integer range 0 to 9 := 0;

begin	
	diz <= std_logic_vector(to_unsigned(compteur_diz,4));

	process (Q, co)
		begin
		if co = '1' then
				if compteur_diz = 9 then
					compteur_diz <= 0;
				else
					compteur_diz <= compteur_diz + 1;
				end if;

			unit <= "0000";
		else 
			unit <= Q;
		end if;
	end process;			



end Behavioral;




--Component ADD3 is
--Port(
--X: In std_logic_vector (3 downto 0);
--Xp3: out std_logic_vector (3 downto 0)); 
--End component;

--signal XT1, RT1:std_logic_vector (3 downto 0);
--Begin
--Xt1 <= ('0',Q(3),Q(2),Q(1)); 
--u1t: ADD3 port map (XT1, RT1); --rt1=xt1+3
--diz <= "000" &RT1(3);
--unit <= (RT1(2), RT1(1), RT1(0), Q(0));