library ieee;
use ieee.std_logic_1164.all;

entity MUX_2_1 is
	port
	(
		S : in    std_logic;
		I : in    std_logic_vector(1 downto 0);
		Y : out   std_logic
	);
end MUX_2_1;

architecture rtl of MUX_2_1 is

begin

	Y <= I(1) when S = '1' else I(0);

end;