library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;

entity tb_MUX_N_1 is
end tb_MUX_N_1;

architecture tb of tb_MUX_N_1 is

	constant N : natural := 17;
	signal S   : std_logic_vector(integer(ceil(log2(real(N)))) - 1 downto 0) := (others => '0');
	signal I   : std_logic_vector(N - 1 downto 0) := (others => '0');
	signal Y   : std_logic := '0';

begin

	I <= "00011110000110010";
	
	process begin
		for i in 0 to 2**10 - 1 loop
			wait for 100 ns;
			if unsigned(S) < N - 1 then
				S <= std_logic_vector(unsigned(S) + 1);
			else
				S <= (others => '0');
			end if;
		end loop;
	end process;

	inst_MUX_N_1 : entity work.MUX_N_1
		generic map
		(
			N => N
		)
		port map
		(
			S => S,
			I => I,
			Y => Y
		);

end;