library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;

entity MUX_N_1 is
	generic
	(
		N : natural
	);
	port
	(
		S : in    std_logic_vector(integer(ceil(log2(real(N)))) - 1 downto 0);
		I : in    std_logic_vector(N - 1 downto 0);
		Y : out   std_logic
	);
end MUX_N_1;

architecture rtl of MUX_N_1 is

	signal Y_to_I  : std_logic_vector(integer(ceil(real(N)/2.0)) - 1 downto 0) := (others => '0');
	signal I_ext   : std_logic_vector(N downto 0) := (others => '0');

begin

	I_ext <= '0' & I;

	GEN_LAYER : if N > 2 generate

		GEN_MUX : for index in 0 to Y_to_I'length - 1 generate

			inst_MUX_2_1 : entity work.MUX_2_1
				port map
				(
					S => S(0),
					I => I_ext(index*2 + 1 downto index*2),
					Y => Y_to_I(index)
				);

		end generate;

		inst_MUX_N_1 : entity work.MUX_N_1
			generic map
			(
				N => Y_to_I'length
			)
			port map
			(
				S => S(S'length - 1 downto 1),
				I => Y_to_I,
				Y => Y
			);

	end generate;
	
	GEN_LAST_LAYER : if N = 2 generate
	
		inst_MUX_2_1 : entity work.MUX_2_1
			port map
			(
				S => S(0),
				I => I,
				Y => Y
			);
	
	end generate;

end;