library ieee;
use ieee.std_logic_1164.all;

entity mar is
	port
	(
		mar_clk                        : in    std_logic;
		mar_clr                        : in    std_logic;
		mar_en                         : in    std_logic;
		mar_datain                     : in    std_logic_vector(3 downto 0);
		mar_dataout                    : out   std_logic_vector(3 downto 0)
	);
end entity;

architecture behavioral of mar is

begin

	process(mar_clk, mar_clr)
	begin
		if mar_clr = '1' then
			mar_dataout <= (others => '0');
		elsif rising_edge(mar_clk) then
			if mar_en = '0' then
				mar_dataout <= mar_datain;
			end if;
		end if;
	end process;

end behavioral;