library ieee;
use ieee.std_logic_1164.all;

entity buffer4 is
	port
	(
		buff4_en                       : in    std_logic;
		datain                         : in    std_logic_vector(3 downto 0);
		dataout                        : out   std_logic_vector(3 downto 0)
	);
end entity;

architecture behavioral of buffer4 is

begin

dataout <= datain when buff4_en = '1' else (others => 'Z');

end behavioral;