library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pc is
    port
	(
        pc_ld                          : in    std_logic;
		pc_en                          : in    std_logic;
		pc_clk                         : in    std_logic;
		pc_rst                         : in    std_logic;
        pc_datain                      : in    std_logic_vector(3 downto 0);
        pc_dataout                     : out   std_logic_vector(3 downto 0)
    );
end entity;

architecture behave of pc is

    signal count                       : unsigned(3 downto 0) := "0001";

begin

    process(pc_clk, pc_rst)
    begin
        if pc_rst = '1' then
            count <= (others => '0');
        elsif rising_edge(pc_clk) then
            if pc_ld = '1' then
                count <= unsigned(pc_datain);
            elsif pc_en = '1' then
				if count < 15 then
					count <= count + 1;
				else
                    count <= (others => '0');
                end if;
            end if;
        end if;
    end process;

    pc_dataout <= std_logic_vector(count);

end behave;