EmbDev.net

Forum: FPGA, VHDL & Verilog Interfacing Nexys2 FPGA with DAC8811 - coding issue


von Divya P. (Company: IIA) (div_01)


Attached files:

Rate this post
useful
not useful
Hi all, I am a newbie to FPGAs and VHDL coding. I am trying to send 
16bit value to the DAC8811 but there seems to be something wrong with my 
code. Can anyone help me out in this?

Thanks & Regards,
Divya

von Lothar M. (lkmiller) (Moderator)


Rate this post
useful
not useful
Divya P. wrote:
> I am trying to send 16bit value to the DAC8811 but there seems to be
> something wrong
What do you expect and what happens instead? Whats the problem and how 
do you recognize it? Whats the according error message and which part of 
the toolchain reports it?

> with my code.
Do not post your Ccode as a picture. Ist quite difficult to copy/paste 
or to edit such a thing. Attrach it as a *.vhdl file instead. And: 
attach the code for the dac_spi component also.

> Can anyone help me out in this?
Did you do a simulation? Is it fine? Add the testbench also.

BTW1: Do you know that indention helps reading and understanding code? 
Its not helpful to start each line at the leftmost position.

BTW2: you do not need any variable here.

BTW3: a bit is defned to have two elements: '0' and '1' (e.g. see 
https://peterfab.com/ref/vhdl/vhdl_renerta/mobile/source/vhd00010.htm).
So its range is '0' to '1'.
What you need to count is an integer in the range from 0 to 15;

: Edited by Moderator
von Divya P. (Company: IIA) (div_01)


Attached files:

Rate this post
useful
not useful
These are the error messages :
ERROR:HDLParsers:164 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 44. parse error, 
unexpected IDENTIFIER
ERROR:HDLParsers:3312 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 45. Undefined 
symbol 'memory_type'.
ERROR:HDLParsers:1209 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 45. memory_type: 
Undefined symbol (last report in this block)
ERROR:HDLParsers:847 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 63. The type of 
the range constraint is not compatible with bit.
ERROR:HDLParsers:3312 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 71. Undefined 
symbol 'i'.
ERROR:HDLParsers:1209 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 71. i: Undefined 
symbol (last report in this block)
ERROR:HDLParsers:854 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 71. The 
expression can not be converted to type std_logic_vector.
ERROR:HDLParsers:808 - 
"D:/Divya_Data/FPGA_related/DAC_8811/DAC_8811.vhd" Line 73. = can not 
have such operands in this context.

von Divya P. (Company: IIA) (div_01)


Rate this post
useful
not useful
Lothar M. wrote:
> BTW3: a bit is defned to have two elements: '0' and '1' (e.g. see
> https://peterfab.com/ref/vhdl/vhdl_renerta/mobile/source/vhd00010.htm).
> So its range is '0' to '1'.
> What you need to count is an integer in the range from 0 to 15;

Thank you for this

von Lothar M. (lkmiller) (Moderator)


Rate this post
useful
not useful
Divya P. wrote:
> These are the error messages
Thats fairly easy, just fix 'em.

The first are lines 44 and 45:

type memory_type is std_logic_vector (0 to 15) of bit;

Where did you find such a thing? Looks for me like you want to have a 16 
bit wide bit vector. And you try to build it out of a std_logic_vector 
somehow...

Why do you not simply use a bit_vector?
https://hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/BitVector.htm


The second error in line 63 (and the following ones) we already had...


BTW: your process "process(clk, rst, daccs, dacsck, dacmosi)" is a kind 
of mess. It is synchronous to clk first (with the "usual 1990-Style 
async reset), but after the synchronous if...endif there comes a 
combinatorial part simply assigning those dac____ signals to other 
signals.

That is very bad design and coding practise. You should do it this way:
1
process(clk, rst) -- never ever more than clk and rst in a sync process!!
2
variable temp : bit; 
3
variable i : integer range 0 to 15 := 0; 
4
begin
5
  if (rst = '1') then   -- hmmmpf... really old-school-style from the 80s
6
    mosi <= '0';
7
    sck <= '0';
8
    cs <= '1';
9
  elsif falling_edge (clk) then
10
    if (rdy = '1') then
11
      pattern <= std_logic_vector(i, 16); 
12
      i := i + 1; 
13
      if (i = 15) then
14
        i := 0;
15
      end if;
16
      dacdata(15 downto 0) <= pattern;
17
    end if;
18
  end if;
19
end process;  -- synchronous proces is done here
20
21
cs <= daccs;  -- concurrent assignments for routing or combinatorial logic
22
sck <= dacsck;
23
mosi <= dacmosi;

A hint: start with a flashing LED, then do some kind of chasing lights. 
Then start your first a real world design. You will crash hopelessly 
when you start with such a SPI interface as first exercise.

: Edited by Moderator
von Divya P. (Company: IIA) (div_01)


Rate this post
useful
not useful
Thank you! That was helpful!

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig