----------------------------------------------------------------------------------
-- Company: IIA
-- Engineer: Divya
-- 
-- Create Date:    11:11:43 12/14/2021 
-- Design Name: 
-- Module Name:    DAC_8811 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_8811 is
port (clk : in std_logic;
      rst : in std_logic;
		sck : out std_logic;
		cs  : out std_logic;
		mosi : out std_logic);
end DAC_8811;

architecture Behavioral of DAC_8811 is
signal rdy, daccs, dacmosi, dacsck : std_logic;
signal dacdata : std_logic_vector (15 downto 0);
signal pattern : std_logic_vector (15 downto 0);
type memory_type is std_logic_vector (0 to 15) of bit; 
signal bits : memory_type := "1001101100101110";
type state_type is (send, stop);
signal state : state_type := send;

component dac_spi
port (clk : in std_logic;
      rst : in std_logic;
		dac_data : in std_logic_vector (15 downto 0);
		mosi : out std_logic;
		cs : out std_logic;
		sck : out std_logic;
		rdy : out std_logic);
end component;

begin
U11 : dac_spi Port map (clk => clk, rst => rst, sck => dacsck, cs => daccs, mosi => dacmosi, dac_data => dacdata, rdy => rdy); 
process(clk, rst, daccs, dacsck, dacmosi)
variable temp : bit; 
variable i : bit range 0 to 15 := 0; 
begin
if (rst = '1') then
mosi <= '0';
sck <= '0';
cs <= '1';
elsif falling_edge (clk) then
if (rdy = '1') then
pattern <= std_logic_vector(i, 16); 
i := i + 1; 
if (i = 15) then
i := 0;
end if;
dacdata(15 downto 0) <= pattern;
end if;
end if;
cs <= daccs;
sck <= dacsck;
mosi <= dacmosi;
end process;
end Behavioral;