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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:11:31 12/15/2021 
-- Design Name: 
-- Module Name:    U11dac_spi - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dac_spi is
port (clk : in std_logic;
      rst : in std_logic;
		cs : out std_logic;
		sck : out std_logic;
		mosi : out std_logic;
		dac_data : in std_logic_vector(15 downto 0);
		rdy : out std_logic);
end dac_spi;

architecture Behavioral of dac_spi is
type state_type is (idle, ready, dummy, send, check);
signal state : state_type; --signal is dependent on the clock cycle and is seen by all the processes
signal dac_send : std_logic_vector (15 downto 0); --assigns dac_send signal for sending 16-bit data
--signal clk_div : std_logic := '0'; 

--start sending data first 
begin
process(dac_data)
begin
for i in 15 downto 0 loop
dac_send(i) <= dac_data(15 - i); --MSB first 
end loop;
end process;

process(clk, rst)
variable index : integer range 0 to 16 := 0; --variable updates immediately  
begin
if(rst = '1') then
index := 0;
elsif falling_edge(clk) then
case state is 
when idle => --idle state : cs is high, sck is low 
sck <= '0';
cs <= '1';
index := 0;
rdy <= '1';
state <= ready;

when ready => --ready state : cs is low, sck is low
rdy <= '0';
cs <= '0';
sck <= '0';
state <= dummy;

when dummy => --during dummy state, send index variable to mosi 
mosi <= dac_send(index);
state <= send;

when send => --during send state, sck is high and the variable index advances by 1 bit
sck <= '1';
state <= check;
index := index + 1;

when check => --during check state, sck is high and all 16 bits shifts to dac register only if the state is in idle
sck <= '1';
if (index = 16) then
state <= idle;
else
state <= ready;
end if;
end case;
end if;
end process;

end Behavioral;