Hi all, I'm new to FPGA but am really motivated to become well-adept in VHDL and FPGA. I am trying to program figure 31 (page 18) shown here: https://www.analog.com/media/en/technical-documentation/data-sheets/AD7352.pdf with the help of the timing specifications on page 5. I think there should be two states: SCLK = High and low and I was thinking about using a shift register to take the input of a vector of bits. But I am having difficulty 1) making the state machine 2) programming it into VHDL. I would appreciate any help!
: Moved by Moderator
Not that hard. Make a simple counter counting for the full cycle. For some time in the cycle toggle SCLK for enough clocks. Maybe 30 clocks will be enough? Also use SCLK to shift in the value from SDATA. At the end of the cycle, when counter is at it's maximum, store the two sample values in the shift register to some other register and set the counter to zero.
So here is the solution: AD7352_sim.vhd simulates the very basic functionality of the ADC. AD7352_read.vhd contains what you intend to do, read data from the ADC. AD7352_bench.vhd connects them both together. Have fun (-: