library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity AD7352_bench is end AD7352_bench; architecture tb of AD7352_bench is component AD7352_sim is Port( CS_n : in std_logic; SCLK : in std_logic; SDATA_A : out std_logic; SDATA_B : out std_logic); end component; component AD7352_read is Port( CLK : in std_logic; CS_n : out std_logic; SCLK : out std_logic; SDATA_A : in std_logic; SDATA_B : in std_logic; NEW_DATA: out std_logic; DATA_A : out std_logic_vector(11 downto 0); DATA_B : out std_logic_vector(11 downto 0)); end component; signal CLK : std_logic:='1'; signal CS_n : std_logic:='1'; signal SCLK : std_logic:='1'; signal SDATA_A : std_logic:='1'; signal SDATA_B : std_logic:='1'; signal NEW_DATA: std_logic:='1'; signal DATA_A : std_logic_vector(11 downto 0):=(others => '0'); signal DATA_B : std_logic_vector(11 downto 0):=(others => '0'); begin CLK <= not CLK after 5 ns; inst_AD7352_sim : AD7352_sim Port map( CS_n => CS_n, SCLK => SCLK, SDATA_A => SDATA_A, SDATA_B => SDATA_B); inst_AD7352_read : AD7352_read Port map( CLK => CLK, CS_n => CS_n, SCLK => SCLK, SDATA_A => SDATA_A, SDATA_B => SDATA_B, NEW_DATA => NEW_DATA, DATA_A => DATA_A, DATA_B => DATA_B); end;