library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all; 

entity AD7352_sim is Port(
	CS_n    : in  std_logic;
	SCLK    : in  std_logic;
	SDATA_A : out std_logic;
	SDATA_B : out std_logic);
end AD7352_sim;

architecture sim of AD7352_sim is

type Rom1kx11 is array (0 to 1023) of unsigned(11 downto 0);
signal Sinus_Rom : Rom1kx11;
signal akku_A: unsigned(15 downto 0):=(others => '0');
signal akku_B: unsigned(15 downto 0):=(others => '0');
signal ADC_A_Samplevalue: integer range 0 to 2**12-1:=0;
signal ADC_B_Samplevalue: integer range 0 to 2**12-1:=0;
signal SDATA_A_SR: std_logic_vector(31 downto 0):=(others => '0');
signal SDATA_B_SR: std_logic_vector(31 downto 0):=(others => '0');
signal bitcounter: integer range 0 to 31:=0;

constant f_step_A: integer:= 2345;
constant f_step_B: integer:= 1234;

begin

table: for i in 0 to 1023 generate
	sinus_rom(I) <= to_unsigned(integer(sin(2.0*MATH_PI*(real(I)+0.5)/1024.0)*(real(2**(11))-0.5))+2**(11),12);
end generate;

SDATA_A <= SDATA_A_SR(bitcounter) when CS_n = '0' else 'Z';
SDATA_B <= SDATA_B_SR(bitcounter) when CS_n = '0' else 'Z';

process (CS_n, SCLK) begin
	if rising_edge(CS_n) then
		akku_A <= akku_A + to_unsigned(f_step_A,16);
		akku_B <= akku_B + to_unsigned(f_step_B,16);
		SDATA_A_SR <= "00" & std_logic_vector(Sinus_Rom(to_integer(akku_A(15 downto 6)))) & "0000" & std_logic_vector(Sinus_Rom(to_integer(akku_B(15 downto 6)))) & "00";
		SDATA_B_SR <= "00" & std_logic_vector(Sinus_Rom(to_integer(akku_B(15 downto 6)))) & "0000" & std_logic_vector(Sinus_Rom(to_integer(akku_A(15 downto 6)))) & "00";
		ADC_A_Samplevalue <= to_integer(Sinus_Rom(to_integer(akku_A(15 downto 6))));
		ADC_B_Samplevalue <= to_integer(Sinus_Rom(to_integer(akku_B(15 downto 6))));
		bitcounter <= 31;
	end if;
	if falling_edge(SCLK) then
		if bitcounter /= 0 then
			bitcounter <= bitcounter -1;
		end if;
	end if;
end process;

end;