library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity AD7352_read is Port( CLK : in std_logic; CS_n : out std_logic; SCLK : out std_logic; SDATA_A : in std_logic; SDATA_B : in std_logic; NEW_DATA: out std_logic; DATA_A : out std_logic_vector(11 downto 0); DATA_B : out std_logic_vector(11 downto 0)); end AD7352_read; architecture rtl of AD7352_read is signal counter: unsigned(7 downto 0):=(others => '0'); signal SR_A : std_logic_vector(31 downto 0):=(others => '0'); signal SR_B : std_logic_vector(31 downto 0):=(others => '0'); begin CS_n <= '1' when counter < 14 else '0'; SCLK <= counter(1) when counter > 15 and counter < 143 else '1'; process begin wait until rising_edge(CLK); if counter < 144 then counter <= counter +1; NEW_DATA <= '0'; if counter(1 downto 0) = "10" then SR_A <= SR_A(30 downto 0) & SDATA_A; SR_B <= SR_B(30 downto 0) & SDATA_B; end if; else counter <= (others => '0'); NEW_DATA <= '1'; DATA_A <= SR_A(11+19 downto 19); DATA_B <= SR_A(11+3 downto 3); end if; end process; end;