Forum: FPGA, VHDL & Verilog washing machine (fsm) controller


von Jad F. (frew)


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this is a vhdl code to implement the states of a washing machine with 
four states namely off, wash, rinse and dry. but have an error when i 
select the simulation option . please help correct code

von Klakx (Guest)


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Usually the error description is very helpful

von Gustl B. (-gb-)


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So, there are many Bugs:

1. Don't write 10ns or 60sec, that causes Warnings, write 10 ns and 60 
sec.
2. outstate is 4 Bits wird, but you assign two Bits outstate <= "00";
3. In machcontroller you use wait Statements, this will not be 
synthesizable. If you have to wait, then use an counter and count so 
many clocks till the time has passed.
4. In testBench many/all signals have no default value. If there is no 
default value, a function like NOT cannot invert the signal because it 
is unknown.
5. In testBench you have a signal named clock, but it does not toggle 
and has no dafault value.

Use:
signal clock: std_logic:='0';

begin

clock <= not clock after 5 ns;

to create an 100 MHz Clock.

6. In testBench strButton is assigned to strSgnl and strSgnl is just at 
one time set to '1' but it is never again set to '0'. So it is like the 
strButton is pressed and pushed down for ever.
7. reset is not used.
8. The signals offSgnl, washSgnl, rinseSgnl and drySgnl are assigned, 
but never used because they are not connected to the machcontroller.

So ... please show/describe what you intend to do.

: Edited by User
von Jad F. (frew)


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Klakx wrote:
> Usually the error description is very helpful
[VRFC 10-1360]Signal cannot be unconstrained
[XSIM 43-3321] static elaboration of top level VHDL design unit test 
bench in library work failed

von Gustl B. (-gb-)


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Hello Jad, i got your message. I will answer here.

Yes, i see you have 4 states. But you have to define

- what has to be done in each state?
- what has to happen in each state, that the statemachine should transit 
to another state?

Jad F. wrote:
> [VRFC 10-1360]Signal cannot be unconstrained
> [XSIM 43-3321] static elaboration of top level VHDL design unit test
> bench in library work failed

Right, you have at least to fix the bugs listed above.

: Edited by User
von Gustl B. (-gb-)


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Hello Jad, i got your message. I will answer here.

Yes, i mentioned counter because you used

when off =>outstate <= "00";  -- off state
wait for 60 sec;

for example. A wait statement cannot be synthesized to FPGA logic. There 
is no such thing as time in an FPGA. If you want to wait for 60 seconds, 
then you have to count so high till the time has passed.

Example:
You have an 100 MHz Clock. Then every clock cycle has a 10 ns duration. 
One step of the counter takes 10 ns. If you want to wait for 60 seconts, 
you have to divede that by 10 ns and get 6000000000. So the counter has 
to count so many times.
6000000000 is
101100101101000001011110000000000 in binary, whis has 33 digits. So you 
may use an unsigned(32 downto 0) for the counter. Because the counter 
starts at zero and not at one, you only have to count up to 5999999999.

Such a counter looks like this:

process (clock) begin
   if rising_edge(clock) then
      if startcount = '1' then
         counter <= (others => '0');
      else
         if counter < 5999999999 then
            counter <= counter +1;
         else
            -- finish! transit to next FSM state or do what you like, 
you have waited for 60 seconds.
         end if;
      end if;
   end if;
end process;

Sure, you can write an extra component for the counter, but for such 
little code an extra component is too much extra work. Also if you write 
the counter in a nice way, then you can reuse this one counter for every 
wait state in your FSM.

: Edited by User

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