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-- Company: 
-- Engineer: 
-- 
-- Create Date: 31.03.2021 13:38:51
-- Design Name: 
-- Module Name: machController - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity machcontroller is
    Port ( clock,reset,strButton : in std_logic;
       outstate: out std_logic_vector(3 downto 0));
       
end machcontroller;

architecture Behavioral of machcontroller is
TYPE state_type IS (off,wash, rinse, dry);
   signal  state   : state_type;
begin
process(clock,reset)
begin
if reset = '1' then state <= off;
elsif (Clock'event and Clock = '1' and reset='0') then
case state is
               when off=>
               state <=wash ; -- from off to wash
               when wash=>
               state <= rinse; -- from wash to rinse
               when rinse=>
               state <= dry;  -- from rinse to dry
               when dry=>
               state <= off;  -- from dry to off
              
             
                     
end case;
end if;
end process;
actstate : process 
begin
  CASE state is
      when off =>outstate <= "00";  -- off state
      wait for 60sec;
      when wash =>outstate<= "01";  -- wash state
      wait for 1200sec;
      when rinse =>outstate<= "10";  -- rinse state
      wait for 600sec;
      when dry =>outstate<= "11";    -- dry state
      wait for 1800sec;
      end case;
      end process;




end Behavioral;