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-- Company: 
-- Engineer: 
-- 
-- Create Date: 31.03.2021 15:32:53
-- Design Name: 
-- Module Name: testBench - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testBench is
--  Port ( );
end testBench;

architecture Behavioral of testBench is


component machcontroller is
    Port ( clock,reset,strButton : in std_logic;
       outstate:out std_logic_vector(3 downto 0));
       
end  component;
signal clock,reset,strSgnl: std_logic;
signal offSgnl,washSgnl,rinseSgnl,drySgnl: std_logic_vector;
begin

uut: machcontroller port map(clock=>clock,reset=>reset,strButton=>strSgnl);

process
begin

wait for 50ns;
strSgnl<='1';
washSgnl<="01";
wait for 50ns;
rinseSgnl<="10";
wait for 50ns;
drySgnl<="11";
wait for 50ns;
offSgnl<="00";
end process;


end Behavioral;