Hi, I am trying to interface Lcd tft display via SPI with my custom board. I'm using Spartan 6 (part number :: XC6SLX9, speed grade :: -2, package :: csg324). My initialization part, data sending part are proper in simulation, but I am not getting any pattern on my Lcd display. Where I suppose to check to debug the error..?? Thanks & Regards, Vijji
vijaya lakshmi wrote: > Where I suppose to check to debug the error..?? First step ist to read the toolchains errors and warnings. If there are any you don't know what they mean and you are unsure about ignoring them, then you must check them thoroughly until you are really sure that you can go on with that message. When simulation is ok, then you must check wether your hardware shows the same behaviour. So a logic analyzer to analyze the data stream would be the best... But keep in mind: its very, very (indeed stupidly) easy to write HDL code that simulates properly and fails on hardware immediately. > Where I suppose to check to debug the error..?? What HDL? Maybe you can simply post those files as *.V or *.VHD attachments here. Its fairly easy to recognize critical parts in a beginners code... ;-)
If there is no output at all, this is caused in the most cases by one of the following reasons: - No clock is available. Make a design that connects the clock signal directly to one of you outputs and check you can see a clock there. - The design is in an continuous reset state due to false polarity of the reset signal. - You forgot to constrain your signals to the correct FPGA pins. Check this first since it may damage your hardware. Are you on an eval platform, or some other hardware? is the board proved to work in general?
Hi Vanvouver, FPGA Board is working fine. I constrained signals properly. I generated reset in the top module itself, I didn't constraint reset signal. The attached file is nothing but waveforms of SPI and fsm_controller. check it once.. Thanks & Regards, K Vijaya Lakshmi
: Edited by User
vijaya lakshmi wrote: > My initialization part, data sending part are proper in simulation So, theres no use in sending screenshots from that. Did you read my post? > check it once.. Against WHAT? No one else but you knows anything about that "LCD with SPI interface". So maybe the timing is ok, or maybe not. Who can know? > check it once.. You should do that. Didn't you?
Hi Lothar, I will do it from scratch . I will keep in mind what you told, As per your suggestion I will use logic analyzer to analyze the data stream . Thanks & Regards, Vijji
Check the lcdtft timing requirements. Maybe you send your spi frames to fast or you need to implement an initialization that your lcd can identify an open communication. I had the same problem with my atmega a few days ago...
Vijaya, as Lothar said, it is useless to post simulator screenshots here as you simulation is working, but your hardware is not. Did you check the presence of a clock signal at the output pins? What kind of clock source are you using in your simulation model and in the real hardware? How do you generate the reset signal, is it from an external pushbutton oder generated from an internal counter? Did you prove there are any signal forms at the FPGA outputs? Did you check whether the clock frequency conforms to the LCD's data sheet?
Hi, I couldn't able to debug my project. The following attached files are related to my project. Kindly, help me to point out the error. Any help would be appreciated. Thanks & Regards, Vijji