`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:24:48 06/28/2016 // Design Name: // Module Name: top // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// `include "def.v" module top( input clk, //input rst, output reg tft_rst, output cs, output mosi, output reg RS, output sclk, output reg [`DATAWIDTH-1:0]data //output reg enable ); //internal signals reg clock =0 ; reg [`SCOUNTBIT-1:0] count =0 ; //reg [`DATAWIDTH-1:0] data ; reg enable ; wire busy ; wire [`DATAWIDTH-1:0] data1 ; wire [`DATAWIDTH-1:0] data2 ; wire RS1 ; wire RS2 ; wire tft_rst1 ; wire tft_rst2 ; wire enable2 ; wire enable1 ; reg rst =0 ; //reg RS ; //assign RS3 = RS ; /*assign data_out = data ;*/ //8 Mhz clock generation always@(posedge clk) begin if(count == `SCOUNT-1) begin count <= 0; clock <= ~clock; end else begin if((count == 2) && clock) rst <= 1; count <= count +1'b1; end end //command control always@(posedge clock) begin if((data1 == 8'h29) && enable1) begin tft_rst <= tft_rst2 ; RS <= RS2 ; data <= data2 ; enable <= enable2 ; end else begin tft_rst <= tft_rst1 ; RS <= RS1 ; data <= data1 ; enable <= enable1 ; end end // Instantiating SPI_Master fsm_spi SPI( .clk (clock) , //input .reset_n (rst) , //input .enable (enable) , //output .data (data) , //output .busy (busy) , //input .sck (sclk) , //input .cs (cs) , //input .mosi (mosi) //input ); //instantiation of Controller FSM_control FSM( .rst (rst) , .tft_rst (tft_rst1), .clk (clock) , .data_in (data1) , .enable (enable1), .busy (busy) , .RS (RS1) ); //instantiation of Controller fsm_controller FSM_LED( .rst (rst) , .tft_reset (tft_rst2), .clk (clock) , .data (data2) , .data1 (data1) , //.data_out (data_out), .enable (enable2), .enable2 (enable1), .busy (busy) , .RS (RS2) ); endmodule