`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 10:13:21 06/27/2016 // Design Name: // Module Name: fsm_controller // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// `include "def.v" module fsm_controller( input rst , input clk , output [`DATAWIDTH-1:0] data , input [`DATAWIDTH-1:0] data1 , //output reg [`DATAWIDTH-1:0] data_out , output reg tft_reset , output reg enable , input enable2 , input busy , output reg RS ); parameter TFT_RESET = 4'b0000, CAS_COMMAND = 4'b0001, CAS_INITIAL_DATA1 = 4'b0010, CAS_INITIAL_DATA2 = 4'b0011, CAS_FINAL_DATA1 = 4'b0100, CAS_FINAL_DATA2 = 4'b0101, RAS_COMMAND = 4'b0110, RAS_INITIAL_DATA1 = 4'b0111, RAS_INITIAL_DATA2 = 4'b1000, RAS_FINAL_DATA1 = 4'b1001, RAS_FINAL_DATA2 = 4'b1010, DUMMY_COMMAND = 4'b1011, DUMMY_DATA = 4'b1100, INITIALIZE_DONE = 4'b1101, DATA_TO_SPI1 = 4'b1110, DATA_TO_SPI2 = 4'b1111; //internal signals reg [3:0] state, next_state ; //reg [`DATAWIDTH:0] array[`ARRAYSIZE-1:0] ; reg [`DATAWIDTH-1:0] data_in = 0 ; reg initial_done = 0 ; reg [`RED-1:0] r = 0 ; reg [`GREEN-1:0] g = 0 ; reg [`BLUE-1:0] b = 0 ; reg [`WCOUNT-1:0] counter = 0 ; assign data = data_in; //counting logic to write data into spi for pattern always@(posedge clk) begin if(~rst) begin r <= 0; g <= 0; b <= 0; counter <= 0; end else if(counter == `DATA2SPI) counter <= 0; else if((state == DATA_TO_SPI2) && busy) begin counter <= counter + 1'b1; r <= counter[15:11]; g <= counter[10:5 ]; b <= counter[4 :0 ]; end end //present state logic always@(posedge clk) begin wait((data1 == 8'h29) && busy); if((data1 == 8'h29) && busy) state <= TFT_RESET; if((enable2 == 1) && (data1 == 8'h29)) state <= next_state; end //next_state logic always@(*) begin case(state) TFT_RESET : if(tft_reset ) next_state = CAS_COMMAND ; CAS_COMMAND : if(busy) next_state = CAS_INITIAL_DATA1 ; CAS_INITIAL_DATA1 : if(busy) next_state = CAS_INITIAL_DATA2 ; CAS_INITIAL_DATA2 : if(busy) next_state = CAS_FINAL_DATA1 ; CAS_FINAL_DATA1 : if(busy) next_state = CAS_FINAL_DATA2 ; CAS_FINAL_DATA2 : if(busy) next_state = RAS_COMMAND ; RAS_COMMAND : if(busy) next_state = RAS_INITIAL_DATA1 ; RAS_INITIAL_DATA1 : if(busy) next_state = RAS_INITIAL_DATA2 ; RAS_INITIAL_DATA2 : if(busy) next_state = RAS_FINAL_DATA1 ; RAS_FINAL_DATA1 : if(busy) next_state = RAS_FINAL_DATA2 ; RAS_FINAL_DATA2 : if(busy) next_state = DUMMY_COMMAND ; DUMMY_COMMAND : if(busy) next_state = DUMMY_DATA ; DUMMY_DATA : if(busy) next_state = INITIALIZE_DONE ; INITIALIZE_DONE : if(initial_done) next_state = DATA_TO_SPI1 ; DATA_TO_SPI1 : if(busy ) next_state = DATA_TO_SPI2 ; else next_state = DATA_TO_SPI1 ; DATA_TO_SPI2 : if(counter == `DATA2SPI) next_state = TFT_RESET ; else if(busy) next_state = DATA_TO_SPI1 ; else next_state = DATA_TO_SPI2 ; default : next_state = CAS_COMMAND ; endcase end //output logic always@(*) begin case(state) TFT_RESET : begin tft_reset = 1 ; end CAS_COMMAND : begin RS = 0 ; data_in = 'h2A ; //array[0] = {RS,data_in} ; //data_out = array[0] ; enable = 0 ; initial_done = 0 ; tft_reset = 1 ; end CAS_INITIAL_DATA1 : begin enable = 0 ; RS = 1 ; data_in = 'h00 ; //array[1] = {RS,data_in} ; end CAS_INITIAL_DATA2 : begin enable = 0 ; RS = 1 ; data_in = 'h00 ; //array[2] = {RS,data_in} ; end CAS_FINAL_DATA1 : begin enable = 0 ; RS = 1 ; data_in = 'h01 ; //array[3] = {RS,data_in} ; end CAS_FINAL_DATA2 : begin enable = 0 ; RS = 1 ; data_in = 'h40 ; //array[4] = {RS,data_in} ; end RAS_COMMAND : begin RS = 0 ; enable = 0 ; data_in = 'h2B ; //array[5] = {RS,data_in} ; end RAS_INITIAL_DATA1 : begin enable = 0 ; RS = 1 ; data_in = 'h00 ; //array[6] = {RS,data_in} ; end RAS_INITIAL_DATA2 : begin enable = 0 ; RS = 1 ; data_in = 'h00 ; //array[7] = {RS,data_in} ; end RAS_FINAL_DATA1 : begin enable = 0 ; RS = 1 ; data_in = 'h01 ; //array[8] = {RS,data_in} ; end RAS_FINAL_DATA2 : begin enable = 0 ; RS = 1 ; data_in = 'hE0 ; //array[9] = {RS,data_in} ; end DUMMY_COMMAND : begin RS = 0 ; enable = 0 ; data_in = 'h2C ; //array[10] = {RS,data_in} ; end DUMMY_DATA : begin RS = 0 ; enable = 0 ; data_in = 'h00 ; enable = 0 ; //array[11] = {RS,data_in} ; end INITIALIZE_DONE : begin initial_done = 1'b1 ; enable = 0 ; //tft_reset = 1'b0 ; end DATA_TO_SPI1 : begin RS = 1 ; data_in = 8'h00 ; enable = 0 ; initial_done = 1'b0 ; end DATA_TO_SPI2 : begin RS = 1 ; data_in = 8'h1F ; enable = 0 ; if(counter == `DATA2SPI) enable = 1 ; end default : begin RS = 0 ; data_in = 'h00 ; enable = 1 ; tft_reset = 1'b0 ; end endcase end endmodule