Cache memory

         if (Valid='1') then

            -- forget about functions the first half year of your VHDL career. 

            -- if you don't want to write the mux inline, then have a look for "components" and "component instantiation"

            DataProc<=mux4x1(Cache_OUT(15 downto 0),Cache_OUT(31 downto 16), Cache_OUT(47 downto 32),Cache_OUT(63 downto 48),Palavra); 

            ...

         else   -- to come here Valid must be '0'

             Valid <= validade(V,TAG1,TAG2); -- 

             if (Valid='1') then -- the following code will NEVER be  "reached", 

                                 -- because a SIGNAL in VHDL behaves not the way you want. 

                                 -- Here /Valid/ is '0', because the "new" value of /Valid/ 

                                 -- is updated at the end of the process.

                 ...