Mionxsq Lopbc wrote:
> but it's not working.
How did you find that out? What do you expect and what do you get?
Just a little hint: VHDL is not C!!!
(I cannot make enough exclamation marks!!)
What you did is a kind of controller that may be working if it is
executed sequentially on a CPU. But it will never work as you expect on
hardware with VHDL. Read my comments...
1 | if (Valid='1') then
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2 | -- forget about functions the first half year of your VHDL career.
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3 | -- if you don't want to write the mux inline, then have a look for "components" and "component instantiation"
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4 | DataProc<=mux4x1(Cache_OUT(15 downto 0),Cache_OUT(31 downto 16), Cache_OUT(47 downto 32),Cache_OUT(63 downto 48),Palavra);
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5 | ...
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6 | else -- to come here Valid must be '0'
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7 | Valid <= validade(V,TAG1,TAG2); --
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8 | if (Valid='1') then -- the following code will NEVER be "reached",
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9 | -- because a SIGNAL in VHDL behaves not the way you want.
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10 | -- Here /Valid/ is '0', because the "new" value of /Valid/
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11 | -- is updated at the end of the process.
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12 | ...
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