library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; entity ram_vhdl is Port ( clk,ativa : in STD_LOGIC; addr : in STD_LOGIC_VECTOR (11 downto 0); din : in STD_LOGIC_VECTOR (15 downto 0); wen : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (15 downto 0)); end ram_vhdl; architecture Behavioral of ram_vhdl is type TRam is array(0 to 4095) of std_logic_vector(15 downto 0); impure function init_bram (ram_file_name : in string) return TRam is file ramfile : text open READ_MODE is ram_file_name; variable line_read : line; variable temp:bit_vector(15 downto 0); variable ram_to_return : TRam; begin for i in TRam'range loop readline(ramfile, line_read); read(line_read, temp); ram_to_return(i):=to_stdlogicvector(temp); end loop; return ram_to_return; end function; signal Ram : TRam := init_bram("MEMRAM.txt"); begin process (clk) begin if (clk'event and clk = '1' and ativa='1' ) then if wen = '1' then Ram(conv_integer(addr)) <= din; end if; dout <= Ram(conv_integer(addr)); end if; end process; end Behavioral;