library ieee ; use ieee.std_logic_1164.all; entity mux2x1 is PORT( muxIn1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); muxIn2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); muxControl : IN STD_LOGIC; muxOut : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END mux2x1; ARCHITECTURE comportamental OF mux2x1 IS BEGIN process(muxIn1,muxIn2,muxControl) begin if muxControl='0' then muxOut<=muxIn1; elsif muxControl='1' then muxOut<=muxIn2; end if; end process; END comportamental;