Help with instruction fetch unit in VHDL

Shay Golan wrote:
> after writing the entire architecture and performing multiple test
> benches
With success?
Was the fetch unit in question also tested?

> we wrote the architecture to an fpga board and... it didn't work.
How many clocks do you have in the whole design?

> Examining things closely, we found out there's something wrong with our
> instruction fetch. mainly, the PC can't advance to the next instruction
> address. I wrote down a simple entity with 2 components - a 32 bits
> register and an adder. the register outputs data (program address) to
> the adder. the adder performs a "+4" on the address and sends it back to
> the PC.
>
> Simple, isn't it?
The task is fairly simple, your solution is very complicated.
Why using a bunch of files for this simple task?
Why implementing an adder and discarding one bit?


> But it's not working, for some reason - when i simulate this unit it
> only has junk on it's bus (XXXXXXXX on modelsim). I can't find the
> problem and i'm desperate.
X means there is more then only one driver on this signal..
And you cannot initialize this here with 0
   signal NextPC :std_logic_vector(N-1 downto 0):=zeroes;
and here:
    dataOut:out std_logic_vector(N-1 downto 0):=zeroes
when it is also at the same time an output with an undefined value here:
    signal Q_tmp: std_logic_vector(N-1 downto 0);
    :
    dataOut <= Q_tmp;

This must be the only place to be initialized:
    signal Q_tmp: std_logic_vector(N-1 downto 0) := (others=>'0');

It took me about 2 minutes to locate this fairly common error because i 
had to dig around in 3 files. Would the complete code (a simple 
registered adder) had been located in 1 file, the you would have seen 
the problem yourself...

> i have attached all the relevant files. can
> someone find what the problem is?
This is not the testbench you used, is it?
Because you will not be able to compile it:

1

    process      -- Start of test bench run:

2

    begin                          

3

    clear <= '0';

4

    wait for 300 ns; 

5

               --------- a endless process?

6

7

end TB;