--------------------------------------------------- -- N-bits Register --------------------------------------------------- -- no enable register library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; -- Include globals use work.global.all; --------------------------------------------------- entity regN is port( dataIn: in std_logic_vector(N-1 downto 0); clock: in std_logic; -- enable: in std_logic; clear: in std_logic; dataOut:out std_logic_vector(N-1 downto 0) ); end regN; ---------------------------------------------------- architecture behv of regN is signal Q_tmp: std_logic_vector(N-1 downto 0); begin process(dataIn, clock, clear) begin if clear = '1' then -- use 'range in signal assigment Q_tmp <= (Q_tmp'range => '0'); elsif (clock='1' and clock'event) then Q_tmp <= dataIn; end if; end process; -- concurrent statement dataOut <= Q_tmp; end behv; ---------------------------------------------------