--------------------------------------------------- -- Fetch segment --------------------------------------------------- -- library ieee ; use ieee.std_logic_1164.all; -- Include globals use work.global.all; --------------------------------------------------- entity fetch is port( clock: in std_logic; clear: in std_logic; datOut:out std_logic_vector(N-1 downto 0) ); end fetch; ---------------------------------------------------- architecture struct of fetch is component regN is port( dataIn: in std_logic_vector(N-1 downto 0):=zeroes; -- "zeroes" is a 32 bit vector of '0's clock: in std_logic; clear: in std_logic; dataOut:out std_logic_vector(N-1 downto 0):=zeroes ); end component; component Adder is port( x: in std_logic_vector(N-1 downto 0); y: in std_logic_vector(N-1 downto 0); Sum: out std_logic_vector(N-1 downto 0) ); end component; signal currPC :std_logic_vector(N-1 downto 0):=zeroes; signal NextPC :std_logic_vector(N-1 downto 0):=zeroes; begin Program_counter: port map regN(NextPC, clock, clear, currPC); Next_IR: port map adder(currPC, four, NextPC); -- "four" is a 32 bits vector with the decimal value of 4 datOut <= NextPC; end struct; ---------------------------------------------------