Search results for "111"

multiple driver error

if (clk'event and clk='1') then if (en = '1' and rd='1' and wr='1' and s2='1' and count1="111" and s1='0' ) then ... [/vhdl] Due to the incomplete sensitivity list your simnulation ist totally crap. And the description of an asynchronous clock enable is very unusual... :-/ This warning

FPGA, VHDL & Verilog ·rajendra soloni ·2011-04-12 21:12 ·4 Replies

Error in VHDL

when "00100000"=> y<="101"; when "01000000"=> y<="110"; when others=> y<="111"; end case; else y<="UUU"; end if; end process; end enc_arc; [/vhdl] this is my code but i get this error message

FPGA, VHDL & Verilog ·vhdl newbie ·2013-09-10 15:05 ·2 Replies

Bit Bang SPI

SD card. How can I bit bang SPI on ARM? I couldn't find SPI bit bang code specifically for ARM/LPC111x. It is simply using bit bang code for AVR/8051/etc? Thanks in advance, John

µC & Digital Electronics ·John ·2011-04-07 18:25 ·2 Replies

RAM overflow is it acceptable

: 32801 from 26624 -------> 123% Number of 4 input LUTs : 29767 from 26624 -------> 111% Number of bonded IOBs : 33 from 221 -------> 14% Number of GCLKs : 2 from 8 ------->25% ------------------------------------------------------------

FPGA, VHDL & Verilog ·Abdallah      ·2014-04-17 16:26 ·4 Replies

Instruction set implementation in VHDL

constant BEQ : std_logic_vector(2 downto 0) := "110"; constant JALR : std_logic_vector(2 downto 0) := "111"; -- SIGNALS DECLARATION signal opcode : std_logic_vector(MAXWIDTH-1 downto MAXWIDTH-3); signal regA : std_logic_vector(MAXWIDTH-4 downto MAXWIDTH-6); signal regB : std_logic_vector(MAXWIDTH

FPGA, VHDL & Verilog ·Maxim Moor ·2015-11-30 19:01 ·8 Replies

Header for PIC16F688 with C-Compiler

digital pin. I don't see it on this chip. As for the configuration bits (what is set in MPLAB, page 111 of datasheet), make sure the watchdog is disabled for now, WDTE, and set FOSC to binary 100. That sets it to use the internal oscillator. Make sure the MCLR pin is pulled to +5 so it doesn't get stuck

µC & Digital Electronics ·Stefan Hölfer ·2013-05-08 17:33 ·3 Replies

need help to modify my code

data = 8'b11100011; 7'b101: data = 8'b00110011; 7'b110: data = 8'b11110111; 7'b111: data = 8'b00111011; 7'b1000: data = 8'b00110001; 7'b1001: data = 8'b00010000; 7'b1010: data = 8'b00100000; 7'b1011: data = 8'b11101101; 7'b1100: data = 8'

= 8'b11110011; 7'b101: weight = 8'b11100110; 7'b110: weight = 8'b11101100; 7'b111: weight = 8'b11110110; 7'b1000: weight = 8'b11111001; 7'b1001: weight = 8'b00000010; 7'b1010: weight = 8'b11111011; 7'b1011: weight = 8'b00001100; 7'b1100:

FPGA, VHDL & Verilog ·shreyas patel ·2013-12-25 11:44 ·0 Replies

M-Bus via Raspberry: reading out ABB B23 meter

my German post which I unfortunately cannot edit anymore. I need to read data from an ABB "B23 111-101" meter which is accessible via an IR-interface on its left side. This IR-interface is configured to M-Bus, 2400 Bd & Address 9 (arbitrary number). For reading from that IF I am using an IR Read

µC & Digital Electronics ·Moadl ·2020-04-27 12:51 ·4 Replies

Resetting Registers on Digital Clock Manager Output

reg [3 : 0] SR; always @ (posedge CLKIN) begin if(RESET) begin SR [3 : 0] <= 4'b111; LOCKED_R <=0; end else begin LOCKED_R <= LOCKED; if(LOCKED < LOCKED_R | STATUS [1] )// H to L LOCKED | CLKIN UNSTABLE SR <= {1'b1 , SR[3 : 1]}; else SR <= {1'b0 , SR[

FPGA, VHDL & Verilog ·Ahmed Abbasi ·2016-11-21 18:00 ·3 Replies

problems with the at91sam7xc getting started example

..\lowlevel.c:102: error: `AT91C_PMC_MOSCS' undeclared (first use in this function) ..\lowlevel.c:111: error: `AT91C_CKGR_USBDIV_1' undeclared (first use in this function) ..\lowlevel.c:112: error: `AT91C_CKGR_OUT_0' undeclared (first use in this function) ..\lowlevel.c:114: error: `AT91C_CKGR_MUL'

µC & Digital Electronics ·Mark D. ·2008-03-06 09:28 ·4 Replies

problem with sinulation in ISE (FPGA)

VHDL coding itself in each entity. The PN generator for Source 1 is initialized with (S2 S1 S0) = 111 and generates PN code 1110100 whereas the PN generator for Source 2 is initialized with (S2 S1 S0) = 110 and generates PN code1101001. so I wrote the sketch I create two inputs one is( CLOCK )

FPGA, VHDL & Verilog ·Zakariya AL-Mazroo'Ee ·2014-06-28 10:00 ·2 Replies

How to do this please

to bus a The return_out output will only be modified when change has a value different from 3'b111. If change is equal to 3'b100, then the return_out output will be equal to the bus formed by the least significant bits of a and b. If change is equal to 3'b001, then the return_out output will

FPGA, VHDL & Verilog ·Berger ·2024-01-10 11:05 ·5 Replies

does vhdl accept this assignment of bits

first_part[/vhdl] contains the copied bits from the stream, signal flag contain the actual no bits, either 111 for 001 or 11 for 01 and [vhdl]signal second_part[/vhdl] contains the final inverted form. Here, i want to ask that if the do the following, would it achieve my purpose without error: [vhdl] first_part

FPGA, VHDL & Verilog ·Amna Khan ·2014-01-06 21:53 ·3 Replies

Weird warning for my design

SCORE_Inter <= DelIy_i_j_1; //C 3'b110: SCORE_Inter <= LUT; //A 3'b111: SCORE_Inter <= 0; //- (output 0) default: SCORE_Inter <= 0; //- (output 0) endcase end endmodule [/code] Based on the attached waveform,the 1st

FPGA, VHDL & Verilog ·dayana42200 ·2018-09-19 02:34 ·17 Replies

Datapath 8 bits VHDL Modelsim

when "101" => f <= a - b; -- substact when "110" => f <= a + 1; -- increment when "111" => f <= a - 1; -- decrement when others => f <= (others => '0'); end case; end process; end behavior; -- shifter .vhd library ieee ; use ieee.std_logic_1164.all ; entity

FPGA, VHDL & Verilog ·KleinBagel ·2018-10-25 21:29 ·6 Replies

VHDL simulation problem-need experts review

; led<="110"; if(bi < 7) then bi:=bi+1; end if; elsif(cyc=20 ) then ack<=sda; bi:=0; led<="111"; elsif (cyc>=21 and cyc<=28 ) then sda<=data(2)(bi); led<="000"; if(bi < 7) then bi:=bi+1; end if; elsif(cyc=29 ) then ack<=sda; led<="001"; elsif(cyc=30 and count >70) then sda<='1'; led

FPGA, VHDL & Verilog ·Shahul Akthar ·2010-07-07 07:15 ·1 Replies

compilation error

Error: ex4.vhd(89): Nonresolved signal 'sel_mux' has multiple sources. # Drivers: # ex4.vhd(111):Statement MUX_DFF # ex4.vhd(96):Conditional signal assignment line__96 # ** Error: ex4.vhd(139): VHDL Compiler exiting # D:/Modeltech_pe_edu_10.2a/win32pe_edu/vcom failed. thanks in advance

FPGA, VHDL & Verilog ·amitai ·2013-05-16 07:24 ·5 Replies

ADC on DEO NANO not working

rising_edge(CLK_50); rst_btn_sr <= rst_btn_sr(1 downto 0) & (NOT BTN_RST); if (rst_btn_sr = "111") then reset_me <= '1'; else reset_me <= '0'; end if; end process reset_btn_proc; --RESET process reset_proc :process begin wait until rising_edge(CLK

FPGA, VHDL & Verilog ·chinmaye ·2018-04-25 01:22 ·3 Replies

Verilog buffer implementation problem

<= 4'b0; FSM_read_state <= ADC_Channel; ADC_CH <= 3'b111; // invalid channel channel_changed <= 1'b0; ch_cng_cnt <= 0; end else begin case(FSM_read_state) ADC_Channel: begin

FPGA, VHDL & Verilog ·H Karim ·2016-03-09 06:36 ·1 Replies

vhdl code simulation

"101", not alu_arm1 when "110", not alu_arm2 when "111", "--------" when others; end behavioral; ----------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all

FPGA, VHDL & Verilog ·Ali abbass Zoraghchian ·2016-08-13 17:35 ·1 Replies

Can't assign value in the register

output reg [2:0]S; always @(posedge CLK) begin if(Resetn == 0) S <= 3'b111; else begin if (Enable == 1) S <= S + 1; end end endmodule module Regn(R, Rin, CLK, Q); input [7:0]R; input Rin, CLK; output reg [7:0]Q;

FPGA, VHDL & Verilog ·Loly Yoshi ·2010-05-01 13:43 ·0 Replies