/*
 * 8-bit UART Transmitter.
 * Able to transmit 8 bits of serial data, one start bit, one stop bit.
 * When transmit is complete {done} is driven high for one clock cycle.
 * When transmit is in progress {busy} is driven high.
 * Clock should be decreased to baud rate.
 */
module Uart_Transmitter (
    input  wire       clk,   // baud rate
    input  wire       start, // start of transaction
    input  wire [7:0] in,    // data to transmit
    output reg        out,   // tx
    output reg        done,  // end of transaction
    output reg        busy   // transaction is in process
);
    
    localparam RESET = 3'b000, IDLE = 3'b001, START_BIT = 3'b010, DATA_BITS = 3'b011, STOP_BIT = 3'b100, DONE = 3'b101;

    reg [2:0] state  = RESET;
    reg [7:0] data   = 8'b0; // to store a copy of input data
    reg [2:0] bitIdx = 3'b0; // for 8-bit data
    reg [1:0] done_delay = 2'b00; // Done signal debouncing

    always @(posedge clk) begin
        case (state)
            RESET: begin // Reset state
                state <= IDLE; // Move to IDLE state after reset
//                out  <= 1'b1;
            end
            IDLE: begin
                done    <= 1'b0; // Ensure done is low in IDLE
                busy    <= 1'b0; 
                bitIdx  <= 3'b0;
                data    <= 8'b0; // Reset data
                if (start) begin
                    data    <= in; // save a copy of input data
                    state   <= START_BIT;
                end
            end
            START_BIT: begin
                out     <= 1'b0; // send start bit (low)
                busy    <= 1'b1;
                done    <= 1'b0;
                state   <= DATA_BITS;
            end
            DATA_BITS: begin // Send 8 data bits
                out     <= data[bitIdx];
                done    <= 1'b0;
                busy    <= 1'b1;
                if (bitIdx == 3'b111) begin
                    bitIdx  <= 3'b0;
                    state   <= STOP_BIT;
                end else begin
                    bitIdx  <= bitIdx + 1'b1;
                end
            end
            STOP_BIT: begin // Send out Stop bit (high)
                out     <= 1'b1; // Send stop bit
                state   <= DONE;
            end
            DONE: begin
                if (done_delay == 2'b11) begin
                    done    <= 1'b1;
                    busy    <= 1'b0;
                    state   <= IDLE;
                end else begin
                    done_delay <= done_delay + 1;
                end
            end
        endcase
    end

endmodule