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Forum: FPGA, VHDL & Verilog Can't assign value in the register


von Loly Y. (Company: loly) (lolyoshi)


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Hi all, I need your help.

This stage includes two 8-to-1 multiplexers, one 9-
bit integer adder, one 1-to-8 demultiplexer, and an
internal register bank. Inputs X0-X4 and X7 are connected
directly to output registers. Inputs X5 and X6 are shifted
with predefined values and are stored in the internal
register bank. The multiplexers select values from the
register bank and feed them into the inputs of the adder.
The demultiplexer distributes output from the adder to
the output registers Y5 and Y6 or send them back to the
register file. The last two cycles are don’t care.

I attach the architecture, the truth table and the simulation of this 
stage

This is my code
1
module Stage2(CLK, Resetn, x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7);
2
  input CLK, Resetn;
3
  input [7:0]x0, x1, x2, x3, x4, x5, x6, x7;
4
  output [7:0]y0, y1, y2, y3, y4, y5, y6, y7;
5
  wire inputEnable;
6
  wire [2:0]S;
7
  wire [5:0]Rout ;
8
  wire [7:0]Rx5, Rx6, outMux1, outMux2, Y, R0, R1, R2, R3;
9
  
10
  assign inputEnable = &S; 
11
  Regn Rgx5(x5, inputEnable, CLK, Rx5); 
12
  Regn Rgx6(x6, inputEnable, CLK, Rx6); 
13
  assign y0 = x0;
14
  assign y1 = x1;
15
  assign y2 = x2;
16
  assign y3 = x3;
17
  assign y4 = x4;
18
  assign y7 = x7;
19
  Counter counter(CLK, 1, Resetn, S);
20
  Multi1 Mux1(Rx5, R0, Rx5, Rx6, R3, Rx6, S[2:0], outMux1);
21
  Multi2 Mux2(Rx5, Rx5, Rx5, Rx6, R1, R2, S[2:0], outMux2);
22
  ALU alu(outMux1, outMux2, S[2], Y);
23
  Decode Dec(S[2:0], Rout);
24
  Regn RgR0(Y, Rout[0], CLK, R0);
25
  Regn RgR1(Y, Rout[1], CLK, R1);
26
  Regn RgR2(Y, Rout[2], CLK, R2);
27
  Regn RgR3(Y, Rout[3], CLK, R3);
28
  Regn Ry5(Y, Rout[4], CLK, y5);
29
  Regn Ry6(Y, Rout[5], CLK, y6);
30
  
31
endmodule
32
module Multi1(R0, R1, R2, R3, R4, R5, sel, bus);
33
  input [2:0]sel;
34
  input [7:0]R0, R1, R2, R3, R4, R5;
35
  output reg[7:0]bus;
36
  
37
  always @(sel)
38
  begin
39
    case(sel)
40
      3'b000:    bus <= R0>>2;
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      3'b010:    bus <= R1;
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      3'b011:    bus <= R2>>2;
43
      3'b100:    bus <= R3>>1;
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      3'b101:    bus <= R4;
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      3'b110:    bus <= R5;
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      default:  bus <= 8'bxxxxxxxx;
47
    endcase
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  end  
49
50
endmodule
51
52
module Multi2(R0, R1, R2, R3, R4, R5, sel, bus);
53
  input [2:0]sel;
54
  input [7:0]R0, R1, R2, R3, R4, R5;
55
  output reg[7:0]bus;
56
57
  always @(sel)
58
  begin
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    case(sel)
60
      3'b000:    bus <= 6>>R0;
61
      3'b001:    bus <= (R1<<5)>>6;
62
      3'b010:    bus <= R2>>3;
63
      3'b011:    bus <= R3>>3;
64
      3'b100:    bus <= R4;
65
      3'b101:    bus <= R5;
66
      default:  bus <= 8'bxxxxxxxx;
67
    endcase
68
  end
69
70
endmodule
71
72
module Counter(CLK, Enable, Resetn, S);
73
  input CLK, Enable, Resetn;
74
  output reg [2:0]S;
75
  
76
  always @(posedge CLK)
77
    begin
78
      if(Resetn == 0)
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        S <= 3'b111;
80
      else
81
      begin
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        if (Enable == 1)
83
          S <= S + 1;
84
      end
85
    end
86
87
endmodule
88
89
module Regn(R, Rin, CLK, Q);
90
  input [7:0]R;
91
  input Rin, CLK;
92
  output reg [7:0]Q;
93
  
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  always @(posedge CLK)
95
    begin
96
      if(Rin)
97
        Q <= R;
98
      else
99
        Q <= Q;
100
    end
101
  
102
endmodule
103
104
module ALU(a, b, sel, x);
105
  input sel;
106
  input [7:0]a, b;  
107
  output [7:0]x;
108
109
  assign x = sel? a-b:a+b;
110
111
endmodule
112
113
module Decode(sel, Rout);
114
  input [2:0]sel;
115
  output reg[5:0]Rout;
116
  
117
  always @(sel)
118
  begin
119
    case(sel)
120
      3'b000:    Rout <= 6'b000001;
121
      3'b001:    Rout <= 6'b000010;
122
      3'b010:    Rout <= 6'b000100;
123
      3'b011:    Rout <= 6'b001000;
124
      3'b100:    Rout <= 6'b010000;
125
      3'b101:    Rout <= 6'b100000;
126
      default:  Rout <= 6'b000000;
127
    endcase
128
  end
129
130
endmodule

My problem is when it calculates the value in Y. It can't assign in R0, 
R1, R2, R3 as I expected

Thank for your help

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