Generic binary decoder in VHDL

Devun R. (devun_rowan) OP (Company: None) 2023-02-23 11:29 #7357222

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I am trying to code a generic one-hot binary decoder in VHDL. The following is the current code that I have come up with:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity address_decoder is

  generic(

    NUM_BITS: natural := 3);

  port(

    input: in std_logic_vector(NUM_BITS - 1 downto 0);

    output: out std_logic_vector((2 ** NUM_BITS) - 1 downto 0));

end address_decoder;

architecture structural of address_decoder is

begin

  G_OUTPUT: for i in 0 to (2 ** NUM_BITS) - 1 generate

    output(i) <= '1' when unsigned(input) = i else '0';

  end generate G_OUTPUT;

end structural;

This code generates a comparator (is-equal) in series with a multiplexer to choose between '0' or '1' according to the output of the comparator for each of the final output bits, as in inferred from the 'when' statement. However, if I use the following architecture, a decoder component will be correctly inferred, but also a latch for the output bits, which I presume is due to incomplete assignment to the output vector.

architecture structural of address_decoder is

  -- Compiler nags the choice must be a constant.

  --output <= (to_integer(unsigned(input)) => '1', others => '0');

  -- Try this incomplete assignment instead.

  output(to_integer(unsigned(input))) <= '1';

end structural;

So my question is, if there is any way to produce only a primitive decoder component without latched output? or the above series of comparators and multiplexers are close enough equivalents of a binary decoder in gate level terms?

Attached files:

decoder_latched_output.png (13 KB)
comp_mux_series.png (22 KB)

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Lothar M. (lkmiller) Moderator (Company: Titel) 2023-02-23 14:09 #7357344

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Devun R. wrote:

but also a latch for the output bits, which I presume is due to incomplete assignment to the output vector.

Your assumption is correct.

What about this:

  process (input) begin

     output <= (others=>'0'); 

     output(to_integer(unsigned(input))) <= '1';  

  end process;

First line in the process is a default assignment, the second overrides the default value because the last assignemt in process "wins".

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Devun R. (devun_rowan) OP (Company: None) 2023-02-24 11:59 #7357935

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Your suggestion produces quite the circuit I expected, but frankly I am self-studying the book "Circuit Design with VHDL" as a beginner and this question is part of the exercises from the chapter dedicated to combinational circuits, hence use of 'process' blocks are shunned throughout the chapter. Anyway, was just wondering if there are more straightforward solutions, and thank you for the hint and snippet explanation.

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Lothar M. (lkmiller) Moderator (Company: Titel) 2023-02-27 11:21 #7359964

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Devun R. wrote:

dedicated to combinational circuits, hence use of 'process' blocks are shunned throughout the chapter.

You mean "concurrent statements"? Because it is absolutely no problem to put combinational circuits (without a clock) into a process.

Anyway, was just wondering if there are more straightforward solutions

Your

output <= (to_integer(unsigned(input)) => '1', others => '0');

is an obviously a valid VHDL solution. The problem is, that only 5% of the whole VHDL syntax elements can be synthesized to hardware. And if so then usually restrictions like a "constant choice value" must be observed. The synthesizers user manual tells you what can be translated to hardware.

This flashing LED is running fine in the simulator:

LED <= not LED after 500 ms;

But the synthesizer will never produce hardware out of this simple line of code.

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