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VHDL is a language that can be used in two ways:

  • As a normal programming language. In this function VHDL is mainly used to simulate the behaviour of digital circuits. The code is compiled and executed by a VHDL simulator.
  • As a hardware description language for ASICs and FPGAs. The fundamental difference here is that you are restricted to a small subset of the language that is understood by the synthesis software.

Basic rules for writing synthesizable VHDL code

VHDL is a very powerful language, but only a small subset is useable (or useful) for writing hardware descriptions that are synthesizable. Especially beginners should follow a few basic rules when writing VHDL code for synthesis:

  • There can only be two types of processes:
    1. purely combinatorial processes (no state memory)
      • all signals that are read in the process must be in the sensitivity list
      • it is not possible to assign a signal to itself or not assign a value to a signal (which would require the signal to remember its previous value)
      • no edge detection (rising_edge(clk), clk'event)
    2. clocked processes with Flip Flops as memory
      • only the clock and an asynchronous reset signal (if necessary) are in the sensitivity list
      • no more than one asynchronous reset
      • only one clock edge detection (rising_edge(clk))
  • only one clock in the whole design, no edge detection on other signals
  • don't divide clocks
  • don't use after, wait for or something similar (can not be synthesized)
  • don't use shared variables
  • only use variables if you fully understand the difference to signals, and you can't solve the problem with signals
  • don't use the old IEEE.STD_LOGIC_(UN)SIGNED packages, instead use the new IEEE.NUMERIC_STD

If you think you can't follow one of these points, there is a good chance you are doing something wrong.

Questions on this topic? Ask them in the FPGA/VHDL Forum