Signal clock generator

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity clock_generator is

    Port ( clk_sel : in STD_LOGIC_VECTOR(3 downto 0);

           clk : out STD_LOGIC);

end clock_generator;

architecture Behavioral of clock_generator is

    signal clk_int : std_logic := '0';

    signal clk_freq : integer := 3;

begin

    clk_gen: process(clk_sel)

    begin

        case clk_sel is

            when "0000" => clk_freq := 3;

            when "0001" => clk_freq := 6;

            when "0010" => clk_freq := 12;

            when "0011" => clk_freq := 24;

            when "0100" => clk_freq := 100;

            when "0101" => clk_freq := 1000;

            when "0110" => clk_freq := 2000;

            when others => null;

        end case;

    end process;

    clk <= not clk_int;

    clk_int_gen: process(clk)

    begin

        clk_int <= not clk_int after (1000000/clk_freq) ns;

    end process;

end Behavioral;