Hi @ all,

Im working with the student version of Modelsim, I have dowloaded the 
latest version (6.5b) and the licence and copied it to the root 
folder(C:\dev\Modeltech_pe_edu_6.5b).

Now to the problem:

Im using "vsim -voptargs=+acc work.tdm_bert_tb" as my run command.
My only error report is:
#Error loading design

Due to the limited content of the error msg I have difficulties finding 
a solution.

What have I already done:
I have reinstalled Modelsim + licence with Administrator rights, tried 
running it with different -commands e.g. vsim -optargs work.tdm_bert_tb, 
vsim work.tdm_bert_tb (none).
I only recieve the above mentoinened error.

Any suggestions are welcome.

Thanks in advance.

Kel.

did you compile your designfiles/tb into the work lib using vlib and 
vcom?

hi,
yes all files including the testbench are compiled.

Hi supachris,
thx for the hint but the only error line I recieve is the "#Error 
loading design" line and no other output. This is the fact that keeps me 
from investigating further.

I am getting the error "Error Load Design"(Modelsim student version).
I have three modules and all are compiling without errors.
However,the order for one of them (test bench) stays '0' in the left 
window.
Now,while trying to run the three modules,I was getting the error which 
I have specified above.

If the topmodule isn't loadable, try the submodules one by one.

Make sure that your PDF student license is contained in the 
C:\Modeltech_pe_edu_10.0c' directory folder only( i.e. is not contained 
in any subfolders, the 'win32pe_edu' folder in particular!). I tried 
this before and it cured the #Error loading system# for me when it 
appeared!

I hope this will cure some headaches aswell!

Regards,
Sentinel.

Hi,

I just had the same error message myself
and this is how I fixed it

#Error loading design

- Check your license is not in a sub folder especially 'win32pe_edu' in 
the  ModelSim directory

- and then check your "tb" design to see if your "module" and "uut" name 
are one and the same for example mine was

         module tb_ex1_gate();

and
         ex1 uut

This led to the error "#Error loading design" because ModelSim could not 
find it in the libraries, it should have been

         module tb_ex1_gate();

and
         ex1_gate uut

also when the this error appears you can find more detail when you 
scroll up on the Transcript section


I hope all this helps I am using ModelSim PE Student Edition 10.0c

Thanks, Christian. Your input has helped me! Cheers..

hi I have same Error which is error loading design
there is no any problem in my code also the licen. file was downloaded 
in my computer but i dont know the problem that make my modelsim doesnot 
run the code is there any one has the solve thanks

This do not solve my problem...

# Compile of TB_Add1b.vhd was successful.
# Compile of Add1b.vhd was successful.
# Compile of config_Add1b.vhd was successful.
# 3 compiles, 0 failed with no errors.

ModelSim > vsim -voptargs=+acc -t ns work.cfg_test
# vsim -voptargs=+acc -t ns work.cfg_test
# Error loading design

Kel wrote:
> hi,
> yes all files including the testbench are compiled.

Loding...

module Alsu8bit (a,b,cin,s3,s2,s1,s0,z);
     input [7:0]a,b;
     input cin,s3,s2,s1,s0;
output [7:0]z;
wire cout;
 wire [7:0] au,lu,shr,shl;
au8bit   au0 (a[7:0],b[7:0],cin,s1,s0,cout,au[7:0]);
lu8bit   lu0(a[7:0],b[7:0],s1,s0,lu[7:0]);
shru8bit shr0 (a[7:0],1'b1,s1,s0,shr[7:0]);
shlu8bit shl0 (a[7:0],1'b1,s1,s0,shl[7:0]);
mux8bit  alsu (au[7:0],lu[7:0],shr[7:0],shl[7:0],s3,s2,z[7:0]);
endmodule

hi,
i got the same error and i saved the license file in 
C:\Modeltech_pe_edu_10.4a . it would be very helpful if anybody let me 
know wht should i do to remove this error

Hello. This is my code of full subtractor using 2 half subtractors. No 
error in compiling. but there is this error will simulating the program:


Port w and d are not found in the connection module.



module hs(diff,borrow,a,b);
  output diff,borrow;
  input a,b;
  assign diff= a^b;
  assign borrow= ~a&b;
endmodule
module fs(diff,borrow,a,b,cin);
  output diff,borrow;
  input a,b,cin;
  wire [1:0]w,d;
  hs a1(.w(w[0]),.a(a),.d(d[0]),.b(b));
  hs a2(.a(d[0]),.d(d[1]),.b(cin),.w(w[1]));
  assign diff=d[1];
  assign borrow= w[0] | w[1];
endmodule


I will be obliged if you could help.

Here's another thought....

I had this problem after moving a simulation folder containing all my 
verilog and project files.  After opening the project file (*.mpf) in a 
text editor, I found all verilog files were described with absolut path 
names, NOT relative path names. A simple find & replace to correct the 
path would fix it!

Joseph wrote:
> Here's another thought....
>
> I had this problem after moving a simulation folder containing all my
> verilog and project files.  After opening the project file (*.mpf) in a
> text editor, I found all verilog files were described with absolut path
> names, NOT relative path names. A simple find & replace to correct the
> path would fix it!

This is the correct fix for most of these errors. It's another one of 
ModelSim's wonderful "quirks", of which there seem to be an infinite 
amount!

* Error: (vsim-3053) C:/Users/Uzma/Desktop/fedup/fsm_tb.v(9): Illegal 
output or inout port connection for "port 'out'".
#

Plz help as i dont understand the meaning of this error.. output port 
has been clearly identified but still its not loading the file...

// My FSM TB Code
module fsm_tb;

reg clk,rst;

reg din;

reg out;

fsm MUT(din,rst,clk,.out(out));

initial

clk<=1;

always

#5 clk <=  ~(clk);

//Set occurance of sequence
initial
begin
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b1 ;

end

endmodule

$ vlog fsm_tb.v
Model Technology ModelSim SE-64 vlog 10.3d Compiler 2014.10 Oct  7 2014
Start time: 12:00:36 on Nov 21,2016
vlog fsm_tb.v
-- Compiling module fsm_tb
** Error: fsm_tb.v(10): near ".": syntax error, unexpected '.', expecting ')'
End time: 12:00:36 on Nov 21,2016, Elapsed time: 0:00:00
Errors: 1, Warnings: 0

After changing ".out(out)" to "my_out(out)", I got the following output:

$ vlog fsm_tb.v
Model Technology ModelSim SE-64 vlog 10.3d Compiler 2014.10 Oct  7 2014
Start time: 12:01:41 on Nov 21,2016
vlog fsm_tb.v
-- Compiling module fsm_tb

Top level modules:
        fsm_tb
End time: 12:01:41 on Nov 21,2016, Elapsed time: 0:00:00
Errors: 0, Warnings: 0

Duke

It worked for me