Hi @ all,
Im working with the student version of Modelsim, I have dowloaded the
latest version (6.5b) and the licence and copied it to the root
Now to the problem:
Im using "vsim -voptargs=+acc work.tdm_bert_tb" as my run command.
My only error report is:
#Error loading design
Due to the limited content of the error msg I have difficulties finding
What have I already done:
I have reinstalled Modelsim + licence with Administrator rights, tried
running it with different -commands e.g. vsim -optargs work.tdm_bert_tb,
vsim work.tdm_bert_tb (none).
I only recieve the above mentoinened error.
Any suggestions are welcome.
Thanks in advance.
I am getting the error "Error Load Design"(Modelsim student version).
I have three modules and all are compiling without errors.
However,the order for one of them (test bench) stays '0' in the left
Now,while trying to run the three modules,I was getting the error which
I have specified above.
Make sure that your PDF student license is contained in the
C:\Modeltech_pe_edu_10.0c' directory folder only( i.e. is not contained
in any subfolders, the 'win32pe_edu' folder in particular!). I tried
this before and it cured the #Error loading system# for me when it
I hope this will cure some headaches aswell!
I just had the same error message myself
and this is how I fixed it
#Error loading design
- Check your license is not in a sub folder especially 'win32pe_edu' in
the ModelSim directory
- and then check your "tb" design to see if your "module" and "uut" name
are one and the same for example mine was
This led to the error "#Error loading design" because ModelSim could not
find it in the libraries, it should have been
also when the this error appears you can find more detail when you
scroll up on the Transcript section
I hope all this helps I am using ModelSim PE Student Edition 10.0c
Guys I solved my problem!
But first lets describe the problem
I was building a half subtractor using structural modelling. One of the
components used a not gate and I named the component "NOTGATE", which
was okay since it compiled peacefully.
But when i simulated the entity, an error occurred that said "Error
I ran a google search and stumbled here. The guy named Christian on this
post pointed out to check the lines above the error "FATAL...". Thanks
I checked mine out and it said that the "entity" NOTGATE was causing
problem which was in the same folder as the entity of half subtractor. I
checked the folder and I remembered "Oh yeah! I had once made that
entity (practicing you know!)." So i went back to my program and renamed
the component NOTGATE as NOTG. Simulated it and it executed without a
1. Read the whole error message not just the error line!
2. Always try to use unique identifiers in you program :/
hi I have same Error which is error loading design
there is no any problem in my code also the licen. file was downloaded
in my computer but i dont know the problem that make my modelsim doesnot
run the code is there any one has the solve thanks
> there is no any problem in my code
You seem to be very confident about that. What gives you that certitude?
>> The guy named Christian on this post pointed out to check the lines>> above the error "FATAL..."
What error messages do you get previous to the fatal error?
This do not solve my problem...
# Compile of TB_Add1b.vhd was successful.
# Compile of Add1b.vhd was successful.
# Compile of config_Add1b.vhd was successful.
# 3 compiles, 0 failed with no errors.
ModelSim > vsim -voptargs=+acc -t ns work.cfg_test
# vsim -voptargs=+acc -t ns work.cfg_test
# Error loading design
Hello. This is my code of full subtractor using 2 half subtractors. No
error in compiling. but there is this error will simulating the program:
Port w and d are not found in the connection module.
assign diff= a^b;
assign borrow= ~a&b;
assign borrow= w | w;
I will be obliged if you could help.
Here's another thought....
I had this problem after moving a simulation folder containing all my
verilog and project files. After opening the project file (*.mpf) in a
text editor, I found all verilog files were described with absolut path
names, NOT relative path names. A simple find & replace to correct the
path would fix it!
Joseph wrote:> Here's another thought....>> I had this problem after moving a simulation folder containing all my> verilog and project files. After opening the project file (*.mpf) in a> text editor, I found all verilog files were described with absolut path> names, NOT relative path names. A simple find & replace to correct the> path would fix it!
This is the correct fix for most of these errors. It's another one of
ModelSim's wonderful "quirks", of which there seem to be an infinite
* Error: (vsim-3053) C:/Users/Uzma/Desktop/fedup/fsm_tb.v(9): Illegal
output or inout port connection for "port 'out'".
Plz help as i dont understand the meaning of this error.. output port
has been clearly identified but still its not loading the file...